Agile verification

Concept

Agile verification refers to processor-verification methodologies intended to address the increasing complexity of modern processor designs (including new ISAs such as RISC-V) by improving verification efficiency and enabling faster coverage convergence. Recent work in this area includes hardware-accelerated frameworks such as TurboFuzz (FPGA-based hardware fuzzing) and DiffTest-H (semantic-aware hardware-accelerated co-simulation), both of which target bottlenecks in existing simulation-based and FPGA/ASIC-based verification flows.

First seen 5/30/2026

Last seen 8/7/2026

Evidence 4 chunks

Wiki v3

WIKI

Agile verification

Definition and motivation

In the provided evidence, agile verification denotes a class of processor-verification methodologies aimed at keeping pace with the growing complexity of modern processor designs and the emergence of new instruction set architectures (ISAs) such as RISC-V. The motivation is twofold:

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

2 connections

TurboFuzz ← implements 95% 4e

TurboFuzz targets agile verification of processors.

DiffTest-H ← mentions 93% 2e

DiffTest-H aims to advance agile verification for processors.

LINKED ENTITIES

2 links

DiffTest-H MENTIONS Extracted graph relationship

TurboFuzz EXAMPLE_OF The TurboFuzz paper title and abstract explicitly position the framework as implementing 'Processor Agile Verification', and the article discusses it as a primary exemplar of the concept.

CITATIONS

7 sources

7 citations — click to expand

[1] Agile verification refers to processor-verification methodologies intended to improve verification efficiency and accelerate coverage convergence in response to increasingly complex designs and new ISAs such as RISC-V. TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification

[2] Existing simulation-based verification approaches incorporating fuzzing suffer from poor performance and inadequate test-case quality, while FPGA/ASIC-accelerated approaches struggle with host-FPGA communication overhead, inefficient test-pattern generation, and suboptimal implementation of the multi-step verification process. TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification

[3] TurboFuzz is an end-to-end hardware-accelerated verification framework that implements the entire Test Generation-Simulation-Coverage Feedback loop on a single FPGA, using optimized seed control flow, inter-seed scheduling, hybrid fuzzer integration, and feedback-driven generation to accelerate coverage convergence. TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification

[4] TurboFuzz achieves up to 2.23x more coverage collection than software-based fuzzers within the same time budget and up to 571x performance speedup when detecting real-world issues, while maintaining full visibility and debugging capabilities with moderate area overhead. TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification

[5] DiffTest-H is a semantic-aware hardware-accelerated co-simulation framework for processor cores, achieving a co-simulation speed of 7.8 MHz on FPGA, and will continue to advance the exploration of agile verification for processors, enhancing the verification efficiency of processor cores. Interpretation of RISC-V Paper: A Semantic-Aware Hardware Acceleration Co-Simulation Verification Framework for Processor Cores - Boardor

[6] DiffTest-H modeled x86-FPGA communication as containing structural, sequential, and behavioral semantics, yielding a semantic-aware communication scheme with approximately 80x improvement over the initial performance and restoring a three-order-of-magnitude improvement compared with pure software simulation. Interpretation of RISC-V Paper: A Semantic-Aware Hardware Acceleration Co-Simulation Verification Framework for Processor Cores - Boardor

[7] DiffTest-H has helped the Xiangshan processor discover and locate over 150 complex bugs across exception/interrupt handling, cache coherence, and vector control logic, resulting in more than 19 PRs and over 780 lines of code modifications, and is open-sourced at https://github.com/OpenXiangShan/difftest with all three MICRO 2025 Artifact Evaluation badges. Interpretation of RISC-V Paper: A Semantic-Aware Hardware Acceleration Co-Simulation Verification Framework for Processor Cores - Boardor