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Agile verification

Concept WIKI v3 · 8/7/2026

Agile verification refers to processor-verification methodologies intended to address the increasing complexity of modern processor designs (including new ISAs such as RISC-V) by improving verification efficiency and enabling faster coverage convergence. Recent work in this area includes hardware-accelerated frameworks such as TurboFuzz (FPGA-based hardware fuzzing) and DiffTest-H (semantic-aware hardware-accelerated co-simulation), both of which target bottlenecks in existing simulation-based and FPGA/ASIC-based verification flows.

Agile verification

Definition and motivation

In the provided evidence, agile verification denotes a class of processor-verification methodologies aimed at keeping pace with the growing complexity of modern processor designs and the emergence of new instruction set architectures (ISAs) such as RISC-V. The motivation is twofold:

  • improve verification efficiency, and
  • enable faster coverage convergence during processor verification.

The TurboFuzz paper frames the demand explicitly: "The increasing complexity of processor designs and the emergence of new instruction set architectures (ISAs) like RISC-V have created demands for more agile and efficient verification methodologies, particularly regarding verification efficiency and faster coverage convergence."

Limits of existing verification approaches

Evidence describes two main families of prior approaches that agile verification seeks to improve upon:

  • Simulation-based approaches that incorporate advanced software-testing techniques such as fuzzing to improve coverage, but suffer from poor performance and inadequate test-case quality when applied to processor verification.
  • Hardware-accelerated solutions using FPGA or ASIC platforms, which still struggle with host-FPGA communication overhead, inefficient test-pattern generation, and suboptimal implementation of the entire multi-step verification process.

Example: TurboFuzz

TurboFuzz is presented as an end-to-end hardware-accelerated verification framework for modern processor verification. It implements the full Test Generation-Simulation-Coverage Feedback loop on a single FPGA. Its key mechanisms include:

  • optimized test-case (seed) control flow,
  • efficient inter-seed scheduling,
  • hybrid fuzzer integration,
  • a feedback-driven generation mechanism to accelerate coverage convergence.

Reported experimental results:

  • up to 2.23x more coverage collection than software-based fuzzers within the same time budget,
  • up to 571x performance speedup when detecting real-world issues,
  • full visibility and debugging capabilities with moderate area overhead.

Example: DiffTest-H

DiffTest-H is described as a semantic-aware hardware-acceleration co-simulation verification framework for processor cores, applied in the development of the open-source high-performance Xiangshan processor.

Key reported characteristics:

  • co-simulation speed of 7.8 MHz on FPGA,
  • a semantic-aware communication scheme that classifies communication between x86 host and Palladium/FPGA into structural, sequential, and behavioral semantics, yielding roughly an 80x improvement over an initial performance baseline,
  • retention of instruction-level error-debugging granularity for better error localization,
  • identification and localization of over 150 complex bugs in the Xiangshan processor across categories such as exception/interrupt handling, cache coherence, and vector control logic, producing more than 19 PRs and over 780 lines of code modifications,
  • open-sourced at https://github.com/OpenXiangShan/difftest and receiving all three MICRO 2025 Artifact Evaluation badges (available, functionally correct, reproducible).

The DiffTest-H description explicitly states that the framework "will continue to advance the exploration of agile verification for processors, enhancing the verification efficiency of processor cores," directly connecting the work to the agile-verification concept.

What the evidence supports

From the provided sources, agile verification is associated with:

  • improving verification efficiency for modern processor designs (including RISC-V cores),
  • accelerating coverage convergence,
  • addressing host-FPGA communication overhead, test-pattern generation, and end-to-end loop implementation in hardware-accelerated processor verification flows,
  • practical use in industrial-grade open-source processors such as Xiangshan.

Related entities

  • TurboFuzz — FPGA-accelerated hardware-fuzzing framework for processor verification, implementing the test-generation/simulation/coverage-feedback loop on a single FPGA.
  • DiffTest-H — Semantic-aware hardware-accelerated co-simulation verification framework used in the Xiangshan processor, described as advancing the exploration of agile verification for processors.

LINKED ENTITIES

2 links
DiffTest-H MENTIONS
TurboFuzz EXAMPLE_OF

CITATIONS

7 sources
7 citations
[1] Agile verification refers to processor-verification methodologies intended to improve verification efficiency and accelerate coverage convergence in response to increasingly complex designs and new ISAs such as RISC-V. TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
[2] Existing simulation-based verification approaches incorporating fuzzing suffer from poor performance and inadequate test-case quality, while FPGA/ASIC-accelerated approaches struggle with host-FPGA communication overhead, inefficient test-pattern generation, and suboptimal implementation of the multi-step verification process. TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
[3] TurboFuzz is an end-to-end hardware-accelerated verification framework that implements the entire Test Generation-Simulation-Coverage Feedback loop on a single FPGA, using optimized seed control flow, inter-seed scheduling, hybrid fuzzer integration, and feedback-driven generation to accelerate coverage convergence. TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
[4] TurboFuzz achieves up to 2.23x more coverage collection than software-based fuzzers within the same time budget and up to 571x performance speedup when detecting real-world issues, while maintaining full visibility and debugging capabilities with moderate area overhead. TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
[5] DiffTest-H is a semantic-aware hardware-accelerated co-simulation framework for processor cores, achieving a co-simulation speed of 7.8 MHz on FPGA, and will continue to advance the exploration of agile verification for processors, enhancing the verification efficiency of processor cores. Interpretation of RISC-V Paper: A Semantic-Aware Hardware Acceleration Co-Simulation Verification Framework for Processor Cores - Boardor
[6] DiffTest-H modeled x86-FPGA communication as containing structural, sequential, and behavioral semantics, yielding a semantic-aware communication scheme with approximately 80x improvement over the initial performance and restoring a three-order-of-magnitude improvement compared with pure software simulation. Interpretation of RISC-V Paper: A Semantic-Aware Hardware Acceleration Co-Simulation Verification Framework for Processor Cores - Boardor
[7] DiffTest-H has helped the Xiangshan processor discover and locate over 150 complex bugs across exception/interrupt handling, cache coherence, and vector control logic, resulting in more than 19 PRs and over 780 lines of code modifications, and is open-sourced at https://github.com/OpenXiangShan/difftest with all three MICRO 2025 Artifact Evaluation badges. Interpretation of RISC-V Paper: A Semantic-Aware Hardware Acceleration Co-Simulation Verification Framework for Processor Cores - Boardor

VERSION HISTORY

v3 · 8/7/2026 · minimax/minimax-m3 (current)
v2 · 6/4/2026 · gpt-5.4-mini
v1 · 5/30/2026 · gpt-5.4