RISC-V
ISARISC-V is a free and open instruction set architecture (ISA) based on RISC principles. The supplied evidence shows it is widely used in verification workflows and is also a target of security research, including surveys on root-of-trust and leakage protection and a paper demonstrating return-oriented programming on RISC-V.
First seen 5/24/2026
Last seen 9/29/2026
Evidence 42 chunks
Wiki v8
WIKI
RISC-V
Overview
RISC-V is a free and open instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. The supplied survey evidence says it has attracted attention in industry and academia and is becoming mainstream. [citation: RISC-V overview and adoption]
NEIGHBORHOOD
2 nodes · 1 edgesgraph · RISC-V · depth=1
RELATIONSHIPS
31 connectionsSpike is the official RISC-V reference simulator.
Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion ← targets ISA 100% 2e
From the title, the study focuses on constrained random verification applied to RISC-V.
RVVTS targets the RISC-V ISA in both RV32 and RV64 configurations.
Its purpose is to generate RISC-V instruction sequences for verification.
The text explicitly identifies BlackParrot as one of the RISC-V cores.
Addresses specification and testing for RISC-V ISA compliance, indicating RISC-V as the target ISA.
Presents a validation suite aimed at the RISC-V ISA.
Renode is cited as a RISC-V ISS used for reference execution, implying it targets RISC-V.
The file is part of a RISC-V-focused build and exercises RISC-V CSRs and trap handling.
Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches ← targets ISA 92% 1e
They apply their approach to a RISC-V core.
Direct mention of the RISC-V Ibex core.
Ibex is a RISC-V core, indicating the code artifact targets/implements the RISC-V instruction set architecture.
The Rocket Core is a RISC-V core, targeting the RISC-V ISA.
The BOOM Core is a RISC-V core, targeting the RISC-V ISA.
The use of riscv-config and discussion of RISC-V CSRs indicate CSRBox targets the RISC-V ISA.
The compiler is specific to the RISC-V instruction set.
All studied designs implement the RISC-V ISA.
It presents a UVM testbench focused on verifying RISC-V instructions.
The Sail RISC-V model (sail-riscv) targets the RISC-V ISA.
RISC-V is among the ISAs across which results are demonstrated.
Icicle is demonstrated on RISC-V among other architectures.
The title explicitly states the case study is for RISC-V.
The title explicitly states the work is for RISC-V.
Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification ← targets ISA 90% 1e
The title ties the mutation-class identification to RISC-V formal verification.
Metamorphic testing for processor verification: A RISC-V case study at the instruction level ← targets ISA 95% 1e
The title denotes a RISC-V case study, confirming the ISA target.
RVX-a tool for concolic testing of embedded binaries targeting RISC-V platforms ← targets ISA 95% 1e
The title explicitly states the tool targets RISC-V platforms.
All evaluated processors are RISC-V cores, indicating the paper’s experiments target RISC-V.
RISE is a RISC-V-based SoC, indicating it targets the RISC-V instruction set.
ProcessorFuzz was evaluated on RISC-V cores, indicating applicability to RISC-V.
The text explicitly identifies Rocket as one of the RISC-V cores.
The text explicitly identifies BOOM as one of the RISC-V cores.
CITATIONS
4 sources4 citations — click to collapse
[1] RISC-V is a free and open RISC-based ISA and is becoming mainstream. A Survey on RISC-V Security: Hardware and Architecture
[2] RISC-V security research includes root-of-trust and anti-tampering/leakage work in IoT contexts. A Survey on RISC-V Security: Hardware and Architecture
[3] RISC-V return-oriented programming can be Turing complete and can perform arbitrary function calls using GNU libc gadgets. Return-Oriented Programming in RISC-V
[4] The CVA6 repository integrates Google ISG (riscv-dv) to create new test programs. Add xrun rules for Google ISG (riscv-dv) (10bfb8db) · Commits · Zhou Maggy / cva6-zicfiss-2025 · GitLab