RISC-V

ISA

RISC-V is a free and open instruction set architecture based on reduced instruction set computer principles. The supplied evidence describes it as a modular ISA defined by RISC-V International and documents its use in processor-verification research, security research, and return-oriented-programming studies.

First seen 5/24/2026

Last seen 5/25/2026

Evidence 8 chunks

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WIKI

RISC-V

Overview

RISC-V is a free and open standard instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. Public reference material describes it as free and open because its specifications are released under permissive open-source licenses and can be implemented without paying royalties. [citation: RISC-V definition]

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NEIGHBORHOOD

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graph · RISC-V · depth=1

LINKED ENTITIES

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RISC-V International defined_by The evidence states that RISC-V is defined by the global nonprofit organization RISC-V International.

CITATIONS

10 sources

10 citations — click to expand

[1] RISC-V definition RISC-V

[2] RISC-V International and modularity Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[3] RV32I example and invalid instructions Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[4] RISC-V verification approaches Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[5] ISS RTL comparison Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[6] Translation buffer Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[7] Execution controller Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[8] Fast Exploration mutation Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[9] RISC-V security survey A Survey on RISC-V Security: Hardware and Architecture

[10] RISC-V ROP Return-Oriented Programming in RISC-V