RISC-V
ISARISC-V is a free and open instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. The supplied evidence describes it as a modular ISA defined by RISC-V International, documents its use in processor-verification research (including random instruction generators such as google/riscv-dv) and security research, and discusses architectural mechanisms such as control and status registers (CSRs), traps and exceptions in machine mode, and leakage-contract verification applied to the RISC-V Ibex core.
First seen 5/24/2026
Last seen 7/19/2026
Evidence 26 chunks
Wiki v7
WIKI
RISC-V
Overview
RISC-V is a free and open standard instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. Public reference material describes it as free and open because its specifications are released under permissive open-source licenses and can be implemented without paying royalties. [citation: RISC-V definition]
NEIGHBORHOOD
4 nodes · 5 edgesgraph · RISC-V · depth=1
RELATIONSHIPS
18 connectionsRVVTS targets the RISC-V ISA in both RV32 and RV64 configurations.
Spike is the official RISC-V reference simulator.
The text explicitly identifies Rocket as one of the RISC-V cores.
The text explicitly identifies BOOM as one of the RISC-V cores.
The text explicitly identifies BlackParrot as one of the RISC-V cores.
Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion ← targets ISA 100% 1e
The study discusses constrained random verification in the context of RISC-V.
Addresses specification and testing for RISC-V ISA compliance, indicating RISC-V as the target ISA.
Presents a validation suite aimed at the RISC-V ISA.
The framework generates instructions for RISC-V processors, indicating its target ISA is RISC-V.
All evaluated processors are RISC-V cores, indicating the paper’s experiments target RISC-V.
Renode is cited as a RISC-V ISS used for reference execution, implying it targets RISC-V.
The file is part of a RISC-V-focused build and exercises RISC-V CSRs and trap handling.
Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches ← targets ISA 92% 1e
They apply their approach to a RISC-V core.
Direct mention of the RISC-V Ibex core.
Ibex is a RISC-V core, indicating the code artifact targets/implements the RISC-V instruction set architecture.
The Rocket Core is a RISC-V core, targeting the RISC-V ISA.
The BOOM Core is a RISC-V core, targeting the RISC-V ISA.
ProcessorFuzz was evaluated on RISC-V cores, indicating applicability to RISC-V.
CITATIONS
9 sources9 citations — click to expand
[1] Leakage contracts for Ibex: formal hardware/software contracts separating hardware and software verification while ensuring interoperability; extended to account for glitches and transitions; first end-to-end verification tool for transient leakage contracts; contracts written in C; applied to RISC-V Ibex core without hardware modifications; proved end-to-end security between masked software and gate-level hardware. Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches
[2] Ibex register-file glitch model: glitches cause one-hot decoded register index transitions to propagate unintended register values; worst case leaks entire register file; x0 is hardwired zero constant, not actual hardware register; each stable index bit halves propagated register values; Ibex register file configurable with 32 registers/5 index bits for RV32I or 16 registers/4 index bits for RV32E. Leakage Contracts for Processors with Transitions and Glitches
[3] Ibex leakage-contract structure: three kinds of leakages (common, writeback, load); common and writeback modeled by regfile_glitches function called regardless of instruction; load leakage modeled by load_leakage function called only during load instructions; glitchy_decode function forms mask of transitioned index bits. Leakage Contracts for Processors with Transitions and Glitches
[4] RISC-V M-mode CSRs and traps: M-mode is highest privilege layer; key CSRs include mstatus (0x300), mtvec (0x305), mepc (0x341), mcause (0x342), mscratch (0x340), mip (0x344), mie (0x304); CSRs are 32-bit accessed with atomic read-modify-write instructions; trap sequence saves PC to mepc, writes cause to mcause, clears MIE, jumps to mtvec; MRET restores PC from mepc, re-enables interrupts. RISC-V From Scratch - Day 21: CSRs, Traps, Exceptions
[5] RISC-V CSR instructions: CSRRW atomically swaps, CSRRS sets bits, CSRRC clears bits. RISC-V From Scratch - Day 21: CSRs, Traps, Exceptions
[6] RISC-V privilege modes: M-mode is highest privilege; S-mode (supervisor) and U-mode (user) added for OS support. RISC-V From Scratch - Day 21: CSRs, Traps, Exceptions
[7] google/riscv-dv is a random instruction generator for RISC-V used in processor verification. GitHub - google/riscv-dv: Random instruction generator for RISC-V
[8] RISC-V security survey: RISC-V community studying security solutions for root of trust and preventing tampering/leakage of sensitive information on RISC-V devices. A Survey on RISC-V Security: Hardware and Architecture
[9] RISC-V ROP: RISC-V return-oriented programming can perform Turing-complete computation and arbitrary function calls using gadgets in GNU libc; compiler converts Turing-complete language code into RISC-V ROP chains. Return-Oriented Programming in RISC-V