Renode

Tool

Renode is Antmicro's open source simulation and virtual development framework for complex embedded systems, used in open source RISC-V verification workflows as a reference instruction set simulator alongside Spike.

First seen 6/25/2026

Last seen 6/25/2026

Evidence 2 chunks

Wiki v1

WIKI

Renode

Renode is an open source simulation and virtual development framework for complex embedded systems, developed and maintained by Antmicro. The project is hosted on GitHub under the repository renode/renode, where it has accumulated a large open source community (thousands of stars and hundreds of forks) and an active update history.

Role in the SystemVerilog / SV Tools ecosystem

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NEIGHBORHOOD

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RELATIONSHIPS

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ISS implements → 84% 1e

Renode is listed as an example of a reference ISS alongside Spike.

RISC-V targets ISA → 76% 1e

Renode is cited as a RISC-V ISS used for reference execution, implying it targets RISC-V.

LINKED ENTITIES

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ISS IMPLEMENTS Extracted graph relationship

RISC-V TARGETS_ISA Extracted graph relationship

CITATIONS

3 sources

3 citations — click to collapse

[1] Renode is Antmicro's open source simulation and virtual development framework for complex embedded systems. renode/renode

[2] Renode is used as a reference RISC-V ISS (instruction set simulator) in the RISCV-DV co-simulation workflow, alongside Spike, with core states compared after each executed instruction. CHIPS Alliance SV Tools Project launch article

[3] The Renode-as-reference-ISS co-simulation setup has been employed in verification of cores such as the VeeR EL2 core and the lowRISC Ibex core. CHIPS Alliance SV Tools Project launch article