Renode

Renode is an open source simulation and virtual development framework for complex embedded systems, developed and maintained by Antmicro. The project is hosted on GitHub under the repository renode/renode, where it has accumulated a large open source community (thousands of stars and hundreds of forks) and an active update history.

Role in the SystemVerilog / SV Tools ecosystem

Renode is referenced in CHIPS Alliance's SV Tools Project article in the context of the RISCV-DV framework, which is a SystemVerilog/UVM-based instruction generator used for verifying RISC-V processors. According to that article, generated instructions are executed by the core under test and simultaneously by a reference RISC-V ISS (instruction set simulator) such as Spike or Renode, and upon completion the core states of both are compared after each executed instruction in terms of register writebacks.

This co-simulation setup, which uses Renode as one of the reference ISS options, has been employed in the verification workflow of multiple cores in the RISC-V ecosystem, including but not limited to the VeeR EL2 core, as well as the Ibex core from lowRISC.

Implementation concepts and target ISA

Renode implements the concept of an Instruction Set Simulator (ISS) — that is, it functionally models the execution of instructions on a target processor so that another implementation (such as an RTL model) can be checked against it. Renode is used as a reference ISS for RISC-V, the open standard instruction set architecture, in the verification flows described above.

See also

• ISS — instruction set simulator concept that Renode implements.
• RISC-V — the instruction set architecture targeted by Renode in the described verification flows.
• RISCV-DV — the SV/UVM-based instruction generator framework that uses Renode as one of its reference ISS options.
• Verible — SystemVerilog parser, linter and formatter toolkit in the SV Tools Project.
• Synlig — SystemVerilog synthesis tool in the SV Tools Project.
• Verilator — open source RTL simulator that has been progressing on UVM support.