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Towards specification and testing of RISC-V ISA compliance

Paper

“Towards specification and testing of RISC-V ISA compliance” is a DATE 2020 paper by Vladimir Herdt, Daniel Große, and Rolf Drechsler. The available evidence identifies it as work on RISC-V ISA compliance specification and testing and shows that it is cited by the RISC-V processor-verification paper “Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study.”

First seen 5/30/2026
Last seen 6/25/2026
Evidence 5 chunks
Wiki v1

WIKI

Overview

“Towards specification and testing of RISC-V ISA compliance” is a paper by Vladimir Herdt, Daniel Große, and Rolf Drechsler, published in DATE 2020. The title identifies the paper’s focus as the specification and testing of compliance with the RISC-V instruction set architecture (ISA).

Bibliographic context

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NEIGHBORHOOD

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RELATIONSHIPS

8 connections
Rolf Drechsler authored by → 100% 2e
Rolf Drechsler is listed as an author of this paper.
Vladimir Herdt authored by → 100% 2e
Vladimir Herdt is listed as an author of this paper.
Daniel Große authored by → 100% 2e
Daniel Große is listed as an author of this paper.
Mutation-based Compliance Testing for RISC-V ← compares with 95% 2e
The paper compares its approach against the specification-based CT from the related paper.
RISC-V targets ISA → 100% 1e
Addresses specification and testing for RISC-V ISA compliance, indicating RISC-V as the target ISA.
Specification-based Test Generation uses → 95% 1e
This paper defines a test-suite specification mechanism and generates compliance tests from it.
Constraint Solving uses → 95% 1e
This paper leverages constraint solving techniques to generate a CT.
The paper cites work on RISC-V ISA compliance testing.

CITATIONS

2 sources
2 citations — click to collapse
[1] The paper is titled “Towards specification and testing of RISC-V ISA compliance,” was published in DATE 2020, and is authored by V. Herdt, D. Große, and R. Drechsler. Efficient Cross-Level Testing for
[2] “Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study” cites “Towards specification and testing of RISC-V ISA compliance” in its references. Efficient Cross-Level Testing for