Rolf Drechsler
PersonRolf Drechsler is represented in the provided evidence through co-authored work on SystemC design, RISC-V virtual prototypes, RISC-V ISA compliance, instruction-set-simulator verification, and RISC-V processor testing.
First seen 5/25/2026
Last seen 8/25/2026
Evidence 35 chunks
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Overview
Rolf Drechsler is represented in the supplied bibliographic evidence as a co-author in system-level design and RISC-V verification research. The evidence includes a 2010 SystemC book, RISC-V virtual-prototype publications from 2018 and 2020, and RISC-V compliance and instruction-set-simulator verification papers from 2019–2020. [C1][C2][C3]
SystemC and system-level design
NEIGHBORHOOD
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27 connectionsRolf Drechsler is affiliated with the University of Bremen
Rolf Drechsler is affiliated with DFKI GmbH
Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← authored by 100% 6e
Rolf Drechsler is listed as an author of the paper.
Rolf Drechsler is listed as an author of this paper.
The paper is authored by Rolf Drechsler.
Rolf Drechsler is listed as an author of the paper.
Rolf Drechsler is listed as an author of the paper.
The paper is authored by Rolf Drechsler.
Rolf Drechsler is listed as an author of this paper.
Improvements paper is co-authored by Rolf Drechsler.
The paper is authored by Rolf Drechsler.
Quality-Driven SystemC Design is co-authored by Rolf Drechsler.
SMT-based stimuli generation paper is co-authored by Rolf Drechsler.
Exploring the Parameter Space for Constrained Random Verification of RISC-V CPUs ← authored by 100% 1e
The paper is authored by Rolf Drechsler.
Rolf Drechsler is listed as co-author of the coverage-driven stimuli generation paper.
Rolf Drechsler is listed as a co-author of the HW/SW Co-Verification paper.
SMT-based Stimuli Generation in SystemC Verification Library (Wille et al., 2009) ← authored by 95% 1e
Rolf Drechsler is listed as a co-author of the SMT-based stimuli generation paper.
Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation ← authored by 97% 1e
Rolf Drechsler is listed as an author of the cross-level verification paper.
The paper is co-authored by Rolf Drechsler
Rolf Drechsler is an author of the RISC-V VP paper.
Rolf Drechsler is listed as an author of the paper.
Security-Aware Benchmarks for Performance Exploration of CHERI-Enabled Architectures ← authored by 100% 1e
Rolf Drechsler is listed as a co-author of the paper.
Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models ← authored by 100% 1e
The paper is authored by Rolf Drechsler
Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion ← authored by 100% 1e
The paper is authored by Rolf Drechsler.
Rolf Drechsler is listed as an author of the paper on CRAVE.
Rolf Drechsler is listed as an author of this paper.
Rolf Drechsler is affiliated with DFKI.
LINKED ENTITIES
6 linksEfficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study AUTHORED_BY Extracted graph relationship
University of Bremen PART_OF Extracted graph relationship
Towards specification and testing of RISC-V ISA compliance AUTHORED_BY Extracted graph relationship
Verifying Instruction Set Simulators using Coverage-guided Fuzzing AUTHORED_BY Extracted graph relationship
Closing the RISC-V compliance gap: Looking from the negative testing side AUTHORED_BY Extracted graph relationship
Extensible and configurable RISC-V based virtual prototype AUTHORED_BY Extracted graph relationship
CITATIONS
4 sources4 citations — click to collapse
[1] D. Große and R. Drechsler authored Quality-Driven SystemC Design, published by Springer in 2010. Efficient Cross-Level Testing for
[2] R. Drechsler is listed as a co-author of the 2018 FDL paper 'Extensible and configurable RISC-V based virtual prototype' and the 2020 JSA paper 'RISC-V based virtual prototype: An extensible and configurable platform for the system-level.' Efficient Cross-Level Testing for
[3] R. Drechsler is listed as a co-author of papers on RISC-V ISA compliance, instruction-set-simulator verification using coverage-guided fuzzing, and the RISC-V compliance gap. Efficient Cross-Level Testing for
[4] The supplied 'Efficient Cross-Level Testing for' source reports finding serious bugs in a pipelined industrial RISC-V TGF-series core, processing more than 200 million instructions per hour, and identifying future work on parallel testing, FPGA use, interrupt-interface testing, ISA extensions, and RTL-specific coverage metrics. Efficient Cross-Level Testing for