Overview

Rolf Drechsler is represented in the supplied bibliographic evidence as a co-author in system-level design and RISC-V verification research. The evidence includes a 2010 SystemC book, RISC-V virtual-prototype publications from 2018 and 2020, and RISC-V compliance and instruction-set-simulator verification papers from 2019–2020. [C1][C2][C3]

SystemC and system-level design

The references in the supplied source list D. Große and R. Drechsler as authors of Quality-Driven SystemC Design, published by Springer in 2010. [C1]

RISC-V virtual prototypes

Drechsler is listed as a co-author of "Extensible and configurable RISC-V based virtual prototype" with Vladimir Herdt, Daniel Große, and Hoang M. Le, published at FDL in 2018. The same reference list also includes "RISC-V based virtual prototype: An extensible and configurable platform for the system-level" by Vladimir Herdt, Daniel Große, Philipp Pieper, and Rolf Drechsler, published in JSA in 2020. [C2]

RISC-V compliance and simulator verification

The evidence lists Drechsler as a co-author of three RISC-V verification-related papers: "Towards specification and testing of RISC-V ISA compliance" at DATE 2020, "Verifying instruction set simulators using coverage-guided fuzzing" at DATE 2019, and "Closing the RISC-V compliance gap: Looking from the negative testing side" at DAC 2020. [C3]

Cross-level RISC-V processor testing context

The supplied source titled "Efficient Cross-Level Testing for" reports a RISC-V processor-testing approach that avoided restrictions on generated instructions, found several serious bugs in a pipelined industrial RISC-V TGF-series core, and processed more than 200 million instructions per hour. Its stated future-work directions included parallelized test sessions with different random seeds, FPGA use, interrupt-interface testing synchronized with instruction-stream co-simulation, additional RISC-V ISA extensions, and new coverage metrics that consider RTL-specific coverage. [C4]