Extensible and configurable RISC-V based virtual prototype
Paper“Extensible and configurable RISC-V based virtual prototype” is a 2018 FDL paper by V. Herdt, D. Große, H. M. Le, and R. Drechsler. Later RISC-V processor-verification work cites it as a source for an open-source RISC-V virtual prototype whose 32-bit RISC-V ISS was used as a reference model in a SystemC-based co-simulation setup.
First seen 5/30/2026
Last seen 5/30/2026
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Extensible and configurable RISC-V based virtual prototype
Overview
“Extensible and configurable RISC-V based virtual prototype” is a paper listed in the references of later RISC-V verification work as: V. Herdt, D. Große, H. M. Le, and R. Drechsler, “Extensible and configurable RISC-V based virtual prototype,” in FDL, 2018, pp. 5–16. [C1]
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4 connectionsThe paper cites the RISC-V VP paper as the source of its ISS reference model.
Vladimir Herdt is an author of the RISC-V VP paper.
Daniel Große is an author of the RISC-V VP paper.
Rolf Drechsler is an author of the RISC-V VP paper.
LINKED ENTITIES
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3 sources3 citations — click to collapse
[1] The paper is listed as V. Herdt, D. Große, H. M. Le, and R. Drechsler, “Extensible and configurable RISC-V based virtual prototype,” in FDL, 2018, pp. 5–16. Efficient Cross-Level Testing for
[2] A later RISC-V verification paper used the 32-bit RISC-V ISS of the open-source RISC-V VP as its ISS reference model and cited references [23] and [24] for that VP. Efficient Cross-Level Testing for
[3] In the later verification setup, the ISS was modified to match the RTL core's supported RISC-V instruction set and CSRs; the RTL core supported RV32I with machine-mode CSRs. Efficient Cross-Level Testing for