Daniel Große
PersonDaniel Große is documented in the supplied evidence through bibliographic entries for work on SystemC design, RISC-V virtual prototyping, RISC-V ISA compliance, instruction set simulator verification, and RISC-V compliance testing.
First seen 5/25/2026
Last seen 6/8/2026
Evidence 7 chunks
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Overview
Daniel Große appears in the supplied evidence as an author or co-author in bibliographic entries connected to SystemC design and RISC-V verification topics. The cited entries include work on RISC-V virtual prototypes, RISC-V ISA compliance, instruction set simulator verification, and compliance-gap analysis.[C1][C2]
Documented publications and topics
NEIGHBORHOOD
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9 connectionsDaniel Große is listed as an author of the paper.
Daniel Große is listed as an author of the paper.
Daniel Große is affiliated with Johannes Kepler University Linz.
Daniel Große is also affiliated with DFKI GmbH.
Daniel Große is listed as an author of the paper.
Daniel Große is an author of the RISC-V VP paper.
Daniel Große is an author of the RISC-V compliance testing paper.
Daniel Große is affiliated with the University of Bremen.
Daniel Große is an author of the negative testing paper.
LINKED ENTITIES
6 linksEfficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study AUTHORED_BY Extracted graph relationship
Johannes Kepler University Linz PART_OF Extracted graph relationship
Towards specification and testing of RISC-V ISA compliance AUTHORED_BY Extracted graph relationship
Verifying Instruction Set Simulators using Coverage-guided Fuzzing AUTHORED_BY Extracted graph relationship
Closing the RISC-V compliance gap: Looking from the negative testing side AUTHORED_BY Extracted graph relationship
Extensible and configurable RISC-V based virtual prototype AUTHORED_BY Extracted graph relationship
CITATIONS
3 sources3 citations — click to collapse
[1] Bibliographic entries list Daniel Große on Quality-Driven SystemC Design and RISC-V virtual-prototype publications. Efficient Cross-Level Testing for
[2] Bibliographic entries list Daniel Große on RISC-V ISA compliance, instruction-set-simulator fuzzing, and RISC-V compliance-gap publications. Efficient Cross-Level Testing for
[3] The cross-level RISC-V testing source reports serious bugs found in an industrial RISC-V TGF series core, throughput above 200 million processed instructions per hour, and future work on parallelism, FPGAs, interrupts, ISA extensions, and coverage metrics. Efficient Cross-Level Testing for