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Johannes Kepler University Linz

Organization

Johannes Kepler University Linz is represented in the provided evidence through complex-systems affiliations for Daniel Große in technical papers on RISC-V processor verification, including cross-level testing and coverage-guided fuzzing approaches at the Register-Transfer Level.

First seen 5/25/2026
Last seen 9/5/2026
Evidence 11 chunks
Wiki v2

WIKI

Overview

Johannes Kepler University Linz appears in the provided technical evidence as an Austrian university affiliation associated with complex-systems research. In one RISC-V processor-verification paper, Daniel Große is listed with the affiliation Chair of Complex Systems, Johannes Kepler University Linz, Austria. In another related processor-verification paper, he is listed with Institute for Complex Systems, Johannes Kepler University Linz, Linz, Austria, alongside a jku.at email address.

Research context in the evidence

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NEIGHBORHOOD

5 nodes · 7 edges
graph · Johannes Kepler University Linz · depth=1

RELATIONSHIPS

8 connections
Daniel Große ← part of 100% 6e
Daniel Grosse is affiliated with Johannes Kepler University Linz and DFKI Bremen.
The paper is produced by authors from Johannes Kepler University Linz.
All authors are affiliated with Johannes Kepler University Linz.
Jonas Reichhardt ← part of 100% 1e
Jonas Reichhardt is affiliated with Johannes Kepler University Linz.
Lucas Klemmer ← part of 100% 1e
Lucas Klemmer is affiliated with Johannes Kepler University Linz.
The paper is affiliated with Johannes Kepler University Linz
FP-RVVTS ← published by 100% 1e
FP-RVVTS was developed and published by researchers at Johannes Kepler University Linz.
Manfred Schlägl ← part of 100% 1e
Manfred Schlägl is affiliated with Johannes Kepler University Linz.

CITATIONS

6 sources
6 citations — click to expand
[1] Daniel Große is listed with the affiliation Chair of Complex Systems, Johannes Kepler University Linz, Austria, in the RISC-V cross-level testing paper. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
[2] The RISC-V cross-level testing paper proposes generating an endless instruction stream during simulation, using an ISS as a reference model, and applying tightly coupled cross-level co-simulation for RTL processor verification. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
[3] The RISC-V cross-level testing paper reports a case study on the 32-bit pipelined RISC-V core of the MINRES The Good Folk Series and states that the approach found several serious bugs. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
[4] Daniel Große is listed with the affiliation Institute for Complex Systems, Johannes Kepler University Linz, Linz, Austria, and the email address daniel.grosse@jku.at in the coverage-guided fuzzing paper. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[5] The coverage-guided fuzzing paper proposes a simulation-based cross-level RTL processor-verification approach that uses coverage-guided fuzzing, an ISS reference model, co-simulation, and custom mutation procedures. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[6] The coverage-guided fuzzing paper reports experiments on the open-source RISC-V-based VexRiscv processor and states that the approach found intricate processor-level bugs. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing