Johannes Kepler University Linz

Organization

Johannes Kepler University Linz is represented in the provided evidence through complex-systems affiliations for Daniel Große in technical papers on RISC-V processor verification, including cross-level testing and coverage-guided fuzzing approaches at the Register-Transfer Level.

First seen 5/25/2026

Last seen 5/30/2026

Evidence 2 chunks

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Overview

Johannes Kepler University Linz appears in the provided technical evidence as an Austrian university affiliation associated with complex-systems research. In one RISC-V processor-verification paper, Daniel Große is listed with the affiliation Chair of Complex Systems, Johannes Kepler University Linz, Austria. In another related processor-verification paper, he is listed with Institute for Complex Systems, Johannes Kepler University Linz, Linz, Austria, alongside a jku.at email address.

Research context in the evidence

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Daniel Große ← part of 100% 2e

Daniel Große is affiliated with Johannes Kepler University Linz.

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CITATIONS

6 sources

6 citations — click to expand

[1] Daniel Große is listed with the affiliation Chair of Complex Systems, Johannes Kepler University Linz, Austria, in the RISC-V cross-level testing paper. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study

[2] The RISC-V cross-level testing paper proposes generating an endless instruction stream during simulation, using an ISS as a reference model, and applying tightly coupled cross-level co-simulation for RTL processor verification. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study

[3] The RISC-V cross-level testing paper reports a case study on the 32-bit pipelined RISC-V core of the MINRES The Good Folk Series and states that the approach found several serious bugs. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study

[4] Daniel Große is listed with the affiliation Institute for Complex Systems, Johannes Kepler University Linz, Linz, Austria, and the email address daniel.grosse@jku.at in the coverage-guided fuzzing paper. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[5] The coverage-guided fuzzing paper proposes a simulation-based cross-level RTL processor-verification approach that uses coverage-guided fuzzing, an ISS reference model, co-simulation, and custom mutation procedures. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[6] The coverage-guided fuzzing paper reports experiments on the open-source RISC-V-based VexRiscv processor and states that the approach found intricate processor-level bugs. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing