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Johannes Kepler University Linz

Organization WIKI v2 · 5/28/2026

Johannes Kepler University Linz is represented in the provided evidence through complex-systems affiliations for Daniel Große in technical papers on RISC-V processor verification, including cross-level testing and coverage-guided fuzzing approaches at the Register-Transfer Level.

Overview

Johannes Kepler University Linz appears in the provided technical evidence as an Austrian university affiliation associated with complex-systems research. In one RISC-V processor-verification paper, Daniel Große is listed with the affiliation Chair of Complex Systems, Johannes Kepler University Linz, Austria. In another related processor-verification paper, he is listed with Institute for Complex Systems, Johannes Kepler University Linz, Linz, Austria, alongside a jku.at email address.

Research context in the evidence

The evidence connects Johannes Kepler University Linz to research on simulation-based processor verification at the Register-Transfer Level (RTL), particularly for RISC-V processors.

Cross-level testing for RISC-V processor verification

The paper "Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study" proposes an efficient cross-level testing approach for processor verification targeting the RISC-V Instruction Set Architecture. The method generates an endless instruction stream during simulation, uses an Instruction Set Simulator (ISS) as a reference model, and runs the ISS with the RTL core under test in a tightly coupled cross-level co-simulation setting. The paper reports a case study on a 32-bit pipelined RISC-V core from the MINRES The Good Folk Series and states that the approach found several serious bugs.

Daniel Große is listed as a coauthor of this work and is affiliated with the Chair of Complex Systems, Johannes Kepler University Linz, Austria.

Coverage-guided fuzzing for cross-level processor verification

The paper "Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing" proposes a simulation-based cross-level approach for RTL processor verification. It applies coverage-guided fuzzing techniques from the software domain to generate processor-level input stimuli, uses an ISS as a reference model in an efficient co-simulation setting, and adds custom mutation procedures tailored to processor verification. The experiments use the open-source RISC-V-based VexRiscv processor and are reported to demonstrate effectiveness in finding intricate processor-level bugs.

Daniel Große is listed as a coauthor of this work with the affiliation Institute for Complex Systems, Johannes Kepler University Linz, Linz, Austria, and also with Cyber-Physical Systems, DFKI GmbH, Bremen, Germany.

Associated person

  • Daniel Große — listed as a coauthor in the provided RISC-V processor-verification papers and affiliated in the evidence with complex-systems units at Johannes Kepler University Linz.

LINKED ENTITIES

1 links
Daniel Große PART_OF

CITATIONS

6 sources
6 citations
[1] Daniel Große is listed with the affiliation Chair of Complex Systems, Johannes Kepler University Linz, Austria, in the RISC-V cross-level testing paper. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
[2] The RISC-V cross-level testing paper proposes generating an endless instruction stream during simulation, using an ISS as a reference model, and applying tightly coupled cross-level co-simulation for RTL processor verification. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
[3] The RISC-V cross-level testing paper reports a case study on the 32-bit pipelined RISC-V core of the MINRES The Good Folk Series and states that the approach found several serious bugs. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
[4] Daniel Große is listed with the affiliation Institute for Complex Systems, Johannes Kepler University Linz, Linz, Austria, and the email address daniel.grosse@jku.at in the coverage-guided fuzzing paper. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[5] The coverage-guided fuzzing paper proposes a simulation-based cross-level RTL processor-verification approach that uses coverage-guided fuzzing, an ISS reference model, co-simulation, and custom mutation procedures. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[6] The coverage-guided fuzzing paper reports experiments on the open-source RISC-V-based VexRiscv processor and states that the approach found intricate processor-level bugs. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

VERSION HISTORY

v2 · 5/28/2026 · gpt-5.5 (current)
v1 · 5/25/2026 · gpt-5.5