Float Fight - Verifying Floating-Point Behavior in RISC-V Simulators
PaperFirst seen 6/10/2026
Last seen 7/19/2026
Evidence 9 chunks
NEIGHBORHOOD
No graph connections found for this entity yet. It may appear in future ingestion runs.
explore full graph →RELATIONSHIPS
20 connectionsThe paper introduces FP-RVVTS as an enhanced version of RVVTS for FP verification.
Katharina Ruep is listed as an author of the paper.
Manfred Schlägl is listed as an author of the paper.
Daniel Große is listed as an author of the paper.
All authors are affiliated with Johannes Kepler University Linz.
The paper evaluates RISC-V VP++ and finds bugs in its FP implementation.
The paper focuses on verifying the RISC-V FP extensions.
The paper employs single-instruction isolation to narrow down failure causes.
The paper measures functional coverage of the generated test sets.
The Float Fight paper cites the Cascade CPU fuzzing paper.
The paper uses FP-RVVTS as its primary verification tool.
The paper evaluates QEMU and finds no failures.
The Float Fight paper cites the randomized testing with direct instruction injection paper.
Comprehensive RISC-V floating-point verification: Efficient coverage models and constraint-based test generation mentions → 100% 1e
The Float Fight paper cites the comprehensive RISC-V FP verification paper.
FloppyFloat: An open source floating point library for instruction set simulators mentions → 100% 1e
The Float Fight paper cites the FloppyFloat paper.
The Float Fight paper cites the RISC-V VP++ paper.
The paper discusses IEEE 754 standard compliance in the context of FP verification.
The paper evaluates Spike FF and finds a flag generation bug.
The paper references and compares against RISCV-DV.
The paper mentions RISCV-DV as related work for RISC-V instruction generation.