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Float Fight - Verifying Floating-Point Behavior in RISC-V Simulators

Paper
First seen 6/10/2026
Last seen 6/10/2026
Evidence 5 chunks

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RELATIONSHIPS

12 connections
Cascade: CPU fuzzing via intricate program generation mentions → 100% 2e
The Float Fight paper cites the Cascade CPU fuzzing paper.
FP-RVVTS introduces → 100% 2e
The paper introduces FP-RVVTS as an enhanced version of RVVTS.
Daniel Große authored by → 100% 1e
The paper is authored by Daniel Große.
Johannes Kepler University Linz published by → 100% 1e
The paper is from Johannes Kepler University Linz.
riscv-dv uses → 90% 1e
The paper references and compares against RISCV-DV.
Randomized Testing of RISC-V CPUs using Direct Instruction Injection mentions → 100% 1e
The Float Fight paper cites the randomized testing with direct instruction injection paper.
Comprehensive RISC-V floating-point verification: Efficient coverage models and constraint-based test generation mentions → 100% 1e
The Float Fight paper cites the comprehensive RISC-V FP verification paper.
FloppyFloat: An open source floating point library for instruction set simulators mentions → 100% 1e
The Float Fight paper cites the FloppyFloat paper.
RISC-V VP++: Next generation open-source virtual prototype mentions → 100% 1e
The Float Fight paper cites the RISC-V VP++ paper.
Katharina Ruep authored by → 100% 1e
The paper is authored by Katharina Ruep.
IEEE 754 standard uses → 95% 1e
The paper discusses IEEE 754 standard compliance in the context of FP verification.
Manfred Schlägl authored by → 100% 1e
The paper is authored by Manfred Schlägl.