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Float Fight - Verifying Floating-Point Behavior in RISC-V Simulators

Paper
First seen 6/10/2026
Last seen 7/19/2026
Evidence 9 chunks

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20 connections
FP-RVVTS introduces → 100% 3e
The paper introduces FP-RVVTS as an enhanced version of RVVTS for FP verification.
Katharina Ruep authored by → 100% 2e
Katharina Ruep is listed as an author of the paper.
Manfred Schlägl authored by → 100% 2e
Manfred Schlägl is listed as an author of the paper.
Daniel Große authored by → 100% 2e
Daniel Große is listed as an author of the paper.
Johannes Kepler University Linz published by → 100% 2e
All authors are affiliated with Johannes Kepler University Linz.
RISC-V VP evaluates → 100% 2e
The paper evaluates RISC-V VP++ and finds bugs in its FP implementation.
RISC-V FP extensions uses → 100% 2e
The paper focuses on verifying the RISC-V FP extensions.
single-instruction isolation uses → 100% 2e
The paper employs single-instruction isolation to narrow down failure causes.
functional coverage measurement uses → 100% 2e
The paper measures functional coverage of the generated test sets.
The Float Fight paper cites the Cascade CPU fuzzing paper.
FP-RVVTS uses → 100% 2e
The paper uses FP-RVVTS as its primary verification tool.
QEMU evaluates → 100% 1e
The paper evaluates QEMU and finds no failures.
The Float Fight paper cites the randomized testing with direct instruction injection paper.
The Float Fight paper cites the comprehensive RISC-V FP verification paper.
The Float Fight paper cites the FloppyFloat paper.
The Float Fight paper cites the RISC-V VP++ paper.
IEEE 754 standard uses → 95% 1e
The paper discusses IEEE 754 standard compliance in the context of FP verification.
Spike FF evaluates → 100% 1e
The paper evaluates Spike FF and finds a flag generation bug.
riscv-dv uses → 90% 1e
The paper references and compares against RISCV-DV.
riscv-dv mentions → 95% 1e
The paper mentions RISCV-DV as related work for RISC-V instruction generation.