FP-RVVTS
ToolFirst seen 6/10/2026
Last seen 8/23/2026
Evidence 20 chunks
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50 connectionsFP-RVVTS evaluates RISC-V VP++ as a DUT.
FP-RVVTS evaluates QEMU as a DUT.
FP-RVVTS evaluates Spike FF as a DUT and identifies bugs in it.
FP-RVVTS uses riscvOVPSim for functional coverage measurement during test-set generation.
FP-RVVTS evaluates Spike as a DUT in its verification flow.
FP-RVVTS configures frm and supports per-instruction rounding mode suffixes.
FP-RVVTS uses strengthened single-instruction isolation to narrow down failures.
FP-RVVTS generates test sets achieving over 95% functional coverage.
FP-RVVTS is an enhanced version of RVVTS extended with FP support.
FP-RVVTS uses Sail RISC-V as the golden reference model for differential verification.
The paper introduces FP-RVVTS as an enhanced version of RVVTS for FP verification.
FP-RVVTS tests DUT configurations that integrate SoftFloat as an FP backend.
FP-RVVTS uses Spike as the golden reference simulator.
FP-RVVTS augments the Instruction Sequence Generator with an FP grammar.
FP-RVVTS supports improved failure cause analysis through isolation techniques.
FP-RVVTS enables comprehensive floating-point verification.
The paper uses FP-RVVTS as its primary verification tool.
FP-RVVTS uses a context-free grammar to specify FP instructions.
FP-RVVTS enriches its grammar with dependency annotations for test reduction.
FP-RVVTS supports negative testing as part of its verification flow.
FP-RVVTS includes improved failure cause analysis.
FP-RVVTS implements Dependency-Based Test-Case Minimization to reduce failures to compact self-contained test cases.
FP-RVVTS introduces and implements Automated Failure Characterization to accelerate root-cause analysis.
FP-RVVTS generates both positive and negative tests for RISC-V FP implementations.
FP-RVVTS implements failure isolation to identify the specific failing instruction.
FP-RVVTS evaluates the PULP ARA RTL implementation as a DUT.
FP-RVVTS uses a context-free grammar with dependency annotations.
FP-RVVTS tests DUT configurations that integrate FloppyFloat as an FP backend.
FP-RVVTS uses functional coverage measurement to guide test-set generation.
FP-RVVTS enriches the grammar with dependency annotations to derive compact test cases.
FP-RVVTS has a Test-Set Generation sub-flow as a primary component.
FP-RVVTS has a Test-Set Execution sub-flow as a primary component.
FP-RVVTS implements a complete flow for floating-point instruction verification.
The FP Grammar Production Rules are a core artifact within the FP-RVVTS framework.
FP-RVVTS identifies and reports NaN handling bugs in simulators.
FP-RVVTS implements grammar-based FP instruction sequence generation for high-coverage test set creation.
FP-RVVTS implements differential execution by comparing DUT outputs against Sail RISC-V reference.
FP-RVVTS supports positive testing as part of its verification flow.
FP-RVVTS evaluates whether simulators are compliant with the RISC-V ISA.
FP-RVVTS paper mentions mutation-based compliance testing as related work.
FP-RVVTS executes tests on a Design Under Test and compares with reference.
FP-RVVTS was authored by Katharina Ruep, Manfred Schlägl, and Daniel Große at Johannes Kepler University Linz.
FP-RVVTS was authored by Manfred Schlägl among others.
FP-RVVTS was authored by Daniel Große among others.
FP-RVVTS was developed and published by researchers at Johannes Kepler University Linz.
FP-RVVTS generates both positive and negative test sets.
RISCV-DV is mentioned as a related tool compared to FP-RVVTS in the context of FP test generation.
FP-RVVTS includes the SailRunner as a dedicated ExecutionRunner component for integrating Sail RISC-V.
Cascade is mentioned as a related processor fuzzer compared to FP-RVVTS.
UVM-Based Verification Environment is compared with FP-RVVTS as a related verification approach for RISC-V FP units.