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Floating-Point Verification

Concept

Floating-point (FP) verification is presented in the evidence as a specialization within processor functional verification and RISC-V instruction-set verification, focused on checking the behavior of FP datapaths, instructions, libraries, and programs. The evidence covers three complementary strands: (1) industrial datapath FP verification using FPgen and Genesys-Pro, (2) RISC-V ISA-level FP verification using tools such as FP-RVVTS and coverage-based test generation, and (3) software program verification using approaches such as Augmented Weak Distance (AWD).

First seen 5/26/2026
Last seen 6/14/2026
Evidence 10 chunks
Wiki v2

WIKI

Overview

Floating-point (FP) verification is presented in the evidence as a specialization within processor functional verification and RISC-V instruction-set verification, focused on checking the behavior of FP datapaths, instructions, libraries, and programs. The evidence covers three complementary strands: (1) industrial datapath FP verification using FPgen and Genesys-Pro [C1-C5], (2) RISC-V ISA-level FP verification using tools such as FP-RVVTS and coverage-based test generation [C6-C9], and (3) software program verification using approaches such as Augmented Weak Distance (AWD) [C10].

Datapath FP verification with FPgen and Genesys-Pro

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RELATIONSHIPS

2 connections
FP-RVVTS ← evaluates 100% 2e
FP-RVVTS enables comprehensive floating-point verification.
Comprehensive RISC-V floating-point verification: Efficient coverage models and constraint-based test generation ← evaluates 100% 1e
This paper addresses comprehensive RISC-V floating-point verification with coverage models.

LINKED ENTITIES

5 links
FP-RVVTS EVALUATES Extracted graph relationship
Comprehensive RISC-V floating-point verification: Efficient coverage models and constraint-based test generation EVALUATES Extracted graph relationship
RVVTS RELATED_TO FP-RVVTS is described as an enhanced version of RVVTS, an open-source framework for positive and negative testing of RISC-V vector instructions that FP-RVVTS extends for FP verification.
Genesys-Pro RELATED_TO Genesys-Pro is documented in the evidence as a test generation system that consumes FPgen-based testing knowledge to produce floating-point verification events, and as the main test generation tool for functional verification of IBM processors.
FPgen RELATED_TO FPgen is cited in the evidence as "A Test Generation Framework for Datapath Floating-Point Verification" and as a source of reusable IEEE floating-point-standard testing knowledge.

CITATIONS

10 sources
10 citations — click to expand
[1] FPgen is described as a Test Generation Framework for Datapath Floating-Point Verification, and its testing knowledge is reusable across IEEE-floating-point-standard-compliant designs. Genesys-Pro: Innovations in Test Program Generation for Functional Verification
[2] FPgen-based testing knowledge can be reused across IEEE floating-point-standard-compliant designs rather than being tied to a single implementation. Genesys-Pro: Innovations in Test Program Generation for Functional Verification
[3] Genesys-Pro consumes FPgen-derived testing knowledge to generate a rich variety of floating-point events, using stream-level and single-instruction generation. Genesys-Pro: Innovations in Test Program Generation for Functional Verification
[4] Genesys-Pro separates test program generation into stream-level and single-instruction levels, and handles bounded FP register resources by injecting load instructions to reload registers with desired values. Genesys-Pro: Innovations in Test Program Generation for Functional Verification
[5] Genesys-Pro was the main test generation tool for functional verification of IBM processors, with reported benefits including higher-quality tests, easier maintenance of different knowledge types, possible full coverage of complex verification plans, and very few or no escape bugs. Genesys-Pro: Innovations in Test Program Generation for Functional Verification
[6] The DATE 2025 paper "Comprehensive RISC-V floating-point verification: Efficient coverage models and constraint-based test generation" (Lu, Liu, Xia, Liu) is cited as a directly related RISC-V FP verification approach using coverage and constraint-based test generation for RV32F. Late Breaking Results: Float Fight - Verifying Floating-Point Behavior in RISC-V Simulators (DATE 2026)
[7] FP-RVVTS is an enhanced version of RVVTS that adds support for the RISC-V FP extensions (F, D, Zfh) through a context-free grammar with annotations, strengthened automatic single-instruction isolation, and improved failure cause analysis. Late Breaking Results: Float Fight - Verifying Floating-Point Behavior in RISC-V Simulators (DATE 2026)
[8] FP-RVVTS uses a context-free FP grammar covering F, D, and Zfh extensions for RV32 and RV64, configures the frm CSR, supports per-instruction rounding-mode suffixes, and uses dependency annotations to produce a minimal system-state snapshot before a failing instruction. Late Breaking Results: Float Fight - Verifying Floating-Point Behavior in RISC-V Simulators (DATE 2026)
[9] On RV64IFD_Zfh across RISC-V VP++ (FF/SF), Spike FF, and QEMU, FP-RVVTS achieves more than 95% functional coverage, and isolated previously unknown bugs including outdated NaN semantics in RISC-V VP++ SF (fmax.d/fmin.d), missing FP-extension-enabled checks in RISC-V VP++ (fld family), incorrect sign-extension in fcvt.wu.d in RISC-V VP++ FF, and a missing underflow flag in fdiv.s in Spike FF. Late Breaking Results: Float Fight - Verifying Floating-Point Behavior in RISC-V Simulators (DATE 2026)
[10] Augmented Weak Distance (AWD) extends the Weak Distance (WD) framework with the Monotonic Convergence Condition and per-path analysis; on 40 SV-COMP 2024 bounds-checking benchmarks it achieves 100% accuracy matching CBMC and is 170× faster on average, while Astrée solves only 17.5%. Augmented Weak Distance for Fast and Accurate Bounds Checking