Overview

Daniel Große appears in the supplied evidence as an author or co-author in bibliographic entries connected to SystemC design and RISC-V verification topics. The cited entries include work on RISC-V virtual prototypes, RISC-V ISA compliance, instruction set simulator verification, and compliance-gap analysis.[C1][C2]

Documented publications and topics

The evidence lists D. Große with Rolf Drechsler as co-author of the Springer book Quality-Driven SystemC Design from 2010.[C1]

In RISC-V virtual prototyping, the evidence cites "Extensible and configurable RISC-V based virtual prototype" by V. Herdt, D. Große, H. M. Le, and R. Drechsler, published at FDL in 2018, and "RISC-V based virtual prototype: An extensible and configurable platform for the system-level" by V. Herdt, D. Große, P. Pieper, and R. Drechsler, published in JSA in 2020.[C1]

For RISC-V compliance and simulator verification, the evidence cites three works listing D. Große among the authors: "Towards specification and testing of RISC-V ISA compliance" at DATE 2020, "Verifying instruction set simulators using coverage-guided fuzzing" at DATE 2019, and "Closing the RISC-V compliance gap: Looking from the negative testing side" at DAC 2020.[C2]

Cross-level RISC-V testing context

The supplied source document on efficient cross-level testing for RISC-V processor verification reports that its approach avoided restrictions on generated instructions, found several serious bugs in a pipelined industrial RISC-V TGF series core, and processed more than 200 million instructions per hour. Its listed future work included parallelized test sessions, FPGA use, interrupt-interface testing, additional RISC-V ISA extensions, and new coverage metrics.[C3]