Vladimir Herdt

Person

Vladimir Herdt is represented in the supplied evidence as an author in RISC-V-focused processor-verification and virtual-prototyping publications, including work on RISC-V ISA compliance, instruction-set-simulator fuzzing, negative compliance testing, cross-level processor testing, and RISC-V virtual prototypes.

First seen 5/25/2026

Last seen 6/8/2026

Evidence 10 chunks

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Overview

Vladimir Herdt is represented in the supplied evidence as an author in RISC-V-focused processor-verification literature. Bibliographic entries in the evidence list Herdt on publications about RISC-V ISA compliance, coverage-guided fuzzing for instruction set simulators, negative testing for RISC-V compliance, and RISC-V virtual prototypes.[1][2]

Work represented in the supplied evidence

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NEIGHBORHOOD

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RELATIONSHIPS

10 connections

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← authored by 100% 6e

Vladimir Herdt is listed as an author of the paper.

DFKI GmbH part of → 100% 5e

Vladimir Herdt is also affiliated with DFKI GmbH.

Verifying Instruction Set Simulators using Coverage-guided Fuzzing ← authored by 100% 5e

Vladimir Herdt is listed as an author of the paper.

University of Bremen part of → 100% 4e

Vladimir Herdt is affiliated with the University of Bremen.

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing ← authored by 100% 2e

Vladimir Herdt is listed as an author of the paper.

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← authored by 100% 2e

Vladimir Herdt is listed as an author of the paper.

Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion ← authored by 100% 1e

The paper is authored by Vladimir Herdt.

Towards specification and testing of RISC-V ISA compliance ← authored by 95% 1e

Vladimir Herdt is an author of the RISC-V compliance testing paper.

Closing the RISC-V compliance gap: Looking from the negative testing side ← authored by 95% 1e

Vladimir Herdt is an author of the negative testing paper.

Extensible and configurable RISC-V based virtual prototype ← authored by 95% 1e

Vladimir Herdt is an author of the RISC-V VP paper.

LINKED ENTITIES

6 links

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study AUTHORED_BY Extracted graph relationship

DFKI GmbH PART_OF Extracted graph relationship

Towards specification and testing of RISC-V ISA compliance AUTHORED_BY Extracted graph relationship

Verifying Instruction Set Simulators using Coverage-guided Fuzzing AUTHORED_BY Extracted graph relationship

Closing the RISC-V compliance gap: Looking from the negative testing side AUTHORED_BY Extracted graph relationship

Extensible and configurable RISC-V based virtual prototype AUTHORED_BY Extracted graph relationship

CITATIONS

4 sources

4 citations — click to collapse

[1] Vladimir Herdt is listed as an author of papers on RISC-V ISA compliance, coverage-guided fuzzing for instruction set simulators, and negative testing for RISC-V compliance. Efficient Cross-Level Testing for

[2] Vladimir Herdt is listed as an author of RISC-V virtual-prototype publications, including an FDL 2018 paper and a 2020 JSA article. Efficient Cross-Level Testing for

[3] The supplied cross-level-testing paper reports finding several serious bugs in a pipelined industrial RISC-V TGF series core and processing more than 200 million instructions per hour. Efficient Cross-Level Testing for

[4] The supplied cross-level-testing paper lists future work on parallelized test sessions, interrupt-interface testing, additional RISC-V ISA extensions, and RTL-specific coverage metrics. Efficient Cross-Level Testing for