Overview

Vladimir Herdt is represented in the supplied evidence as an author in RISC-V-focused processor-verification literature. Bibliographic entries in the evidence list Herdt on publications about RISC-V ISA compliance, coverage-guided fuzzing for instruction set simulators, negative testing for RISC-V compliance, and RISC-V virtual prototypes.[1][2]

Work represented in the supplied evidence

RISC-V compliance and negative testing

The evidence lists “Towards specification and testing of RISC-V ISA compliance” as a DATE 2020 paper by V. Herdt, D. Große, and R. Drechsler. It also lists “Closing the RISC-V compliance gap: Looking from the negative testing side” as a DAC 2020 paper by the same three authors.[1]

Instruction-set-simulator verification

The evidence lists “Verifying instruction set simulators using coverage-guided fuzzing” as a DATE 2019 paper by V. Herdt, D. Große, H. M. Le, and R. Drechsler, with pages 360–365 given in the reference entry.[1]

RISC-V virtual prototypes

The evidence lists “Extensible and configurable RISC-V based virtual prototype” as an FDL 2018 paper by V. Herdt, D. Große, H. M. Le, and R. Drechsler, with pages 5–16. It also lists a 2020 JSA article titled “RISC-V based virtual prototype: An extensible and configurable platform for the system-level” by V. Herdt, D. Große, P. Pieper, and R. Drechsler.[2]

Cross-level processor testing

The supplied cross-level-testing paper excerpt reports an approach that avoided restrictions on generated instructions, found several serious bugs in a pipelined industrial RISC-V TGF series core, and processed more than 200 million instructions per hour.[3] The same excerpt lists future work including parallelized test sessions, interrupt-interface testing, evaluation on additional RISC-V ISA extensions, and new coverage metrics that include RTL-specific coverage.[4]