Extensible and configurable RISC-V based virtual prototype

Overview

“Extensible and configurable RISC-V based virtual prototype” is a paper listed in the references of later RISC-V verification work as: V. Herdt, D. Große, H. M. Le, and R. Drechsler, “Extensible and configurable RISC-V based virtual prototype,” in FDL, 2018, pp. 5–16. [C1]

The available evidence identifies the paper as one of the sources for an open-source RISC-V virtual prototype (RISC-V VP). In a later RISC-V processor-verification case study, the authors used the 32-bit RISC-V ISS from that open-source RISC-V VP as the instruction-set-simulator reference model. [C2]

Technical relevance in later verification work

A later paper, “Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study,” cites this FDL 2018 paper as reference [23] and cites a related 2020 JSA paper as reference [24] for the RISC-V VP. In that later setup, the authors obtained a Verilog RTL implementation from SpinalHDL, converted it to C++ with Verilator, and embedded it in a SystemC-based co-simulation testbench. The RISC-V VP's 32-bit ISS was used as the reference model. [C2]

For that verification use case, the ISS was modified to match the RTL core's supported RISC-V instruction set and CSRs. The RTL core in the cited evaluation supported RV32I together with machine-mode CSRs. [C3]

Scope of evidence

The provided evidence supports the paper's bibliographic identity, authorship, venue, page range, and its later citation as a source for an open-source RISC-V VP and 32-bit RISC-V ISS. It does not provide enough detail to describe the internal architecture, supported devices, configuration mechanisms, license, or implementation details of the 2018 virtual-prototype paper beyond that later use.