Security-Aware Benchmarks for Performance Exploration of CHERI-Enabled Architectures
PaperFirst seen 7/6/2026
Last seen 7/6/2026
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18 connectionsThe paper leverages TestRIG as the basis for security-aware benchmark generation.
The paper applies security-aware post-processing to transform TestRIG output into valid CHERI benchmarks.
The paper evaluates an IMC-based acceleration of CHERI tagged memory using the generated benchmarks.
The paper evaluates the CHERI extension integrated into the RISC-V VP to assess IMC-based acceleration.
The paper uses constrained random instruction generation via TestRIG to produce instruction streams.
The paper uses a virtual prototype to evaluate the generated benchmarks and the IMC acceleration.
The paper targets performance-driven design space exploration for secure embedded architectures.
The paper discusses memory safety as a motivation for CHERI and the benchmarks.
The paper introduces a set of open-source security-aware benchmarks for CHERI-based RISC-V systems.
The paper discusses existing benchmark suites and the need for CHERI-specific ones.
Sayak Deb is listed as a co-author of the paper.
Khushboo Qayyum is listed as a co-author of the paper.
Sallar Ahmadi-Pour is listed as a co-author of the paper.
Christoph Luth is listed as a co-author of the paper.
Rolf Drechsler is listed as a co-author of the paper.
The paper is affiliated with the University of Bremen.
The paper is affiliated with DFKI.
Spandan Das is listed as a co-author of the paper.