Overview

“Towards specification and testing of RISC-V ISA compliance” is a paper by Vladimir Herdt, Daniel Große, and Rolf Drechsler, published in DATE 2020. The title identifies the paper’s focus as the specification and testing of compliance with the RISC-V instruction set architecture (ISA).

Bibliographic context

The paper appears as reference [11] in the bibliography of “Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study.” In that bibliography, it is listed as:

V. Herdt, D. Große, and R. Drechsler, “Towards specification and testing of RISC-V ISA compliance,” in DATE, 2020.

The same reference section also lists other RISC-V verification and compliance resources, including RISC-V ISA tests, the RISC-V compliance task group, the RISC-V torture test generator, RISCV-DV, riscv-formal, and the Sail RISC-V model; however, the available evidence only directly supports the bibliographic facts above for this paper.