RISC-V

Overview

RISC-V is a free and open instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. The supplied survey evidence says it has attracted attention in industry and academia and is becoming mainstream. [citation: RISC-V overview and adoption]

Verification and security context

Public evidence shows RISC-V is used in verification workflows. A CVA6 commit adds rules for the Google instruction stream generator (RISCV-DV) to create new test programs and generate google-riscv-dv assembly outputs. [citation: riscv-dv test-program generation]

Security research in the supplied evidence includes a survey describing work on root of trust and protections against tampering or leakage on RISC-V IoT devices, as well as a paper showing that RISC-V return-oriented programming can be Turing complete and can perform arbitrary function calls using GNU libc gadgets. [citation: RISC-V security survey; RISC-V ROP]