RISC-V
Overview
RISC-V is a free and open standard instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. Public reference material describes it as free and open because its specifications are released under permissive open-source licenses and can be implemented without paying royalties. [citation: RISC-V definition]
A processor-verification paper further describes RISC-V as a free and open ISA defined by the global nonprofit organization RISC-V International. The same source states that a major design goal was to make the ISA suitable for nearly any computing device, and that this goal is reflected in RISC-V's modular design. [citation: RISC-V International and modularity]
ISA configuration in verification examples
The supplied verification evidence uses an RV32I example to show how instruction validity depends on the selected RISC-V configuration. In that example, LWU is described as a pure RV64I instruction and therefore invalid in RV32I, causing an instruction set simulator (ISS) to raise an illegal-instruction exception. The same example shows c.slli x6, 9 raising an illegal-instruction exception when compressed instructions are disabled. [citation: RV32I example and invalid instructions]
This example illustrates that RISC-V verification must account for more than a raw instruction stream: the active ISA configuration, including 32-bit versus 64-bit behavior and whether compressed instructions are enabled, affects whether an instruction is legal. [citation: RV32I example and invalid instructions]
Processor-verification context
RISC-V is a common target for processor-verification research. The cited cross-level verification work lists several RISC-V verification approaches, including semi hand-written directed test suites covering different RISC-V instruction sets, simulation-based generation from randomized patterns or constraint-based specifications, LLVM libFuzzer-based coverage-guided fuzzing for RISC-V ISS verification, and cross-level co-simulation approaches for RTL verification. [citation: RISC-V verification approaches]
The same work presents a co-simulation-oriented fuzzing setup in which an ISS and an RTL processor core are fed the same instruction stream and checked for functional mismatches. Because a pipelined RTL core can fetch and complete instructions differently from an ISS, the paper emphasizes comparing architectural register values at appropriate synchronization points, especially after instructions have completed and register values have changed. [citation: ISS RTL comparison]
Translation buffer and endless instruction streams
In the cited fuzzing approach, test vectors are interpreted as arbitrary endless instruction streams. A translation buffer caches already fetched instructions so that the ISS and RTL core receive the same instruction stream despite different fetch behavior. The paper's example uses a 160-bit test vector divided into five 32-bit instruction entries. [citation: Translation buffer]
Execution controller
The cited execution controller has two purposes: preventing infinite loops and detecting mismatches between processor cores. It conservatively detects an infinite loop when a new program-counter address equals an already executed address and register values are unchanged, and it also applies a hard limit of 10,000 ISS instruction executions. For mismatch detection, it compares registers after register-value changes; in the example, an RTL core erroneously executes LWU x8, x0, 48, causing a mismatch against ISS behavior and stopping the simulation. [citation: Execution controller]
Fuzzer mutations
The same paper describes problem-specific mutations for AFL-based fuzzing. Its "Fast Exploration" phase inserts each RISC-V instruction at the beginning of every test vector with source and destination register arguments fixed to x0 and immediate values fixed to 0; the paper gives addi x0, x0, 0 as an example. [citation: Fast Exploration mutation]
Security research context
Public research context characterizes RISC-V as increasingly important in embedded and IoT settings, where data security and privacy are major concerns. A survey on RISC-V security states that the RISC-V community is studying security solutions aimed at establishing a root of trust and preventing sensitive information on RISC-V devices from being tampered with or leaked. [citation: RISC-V security survey]
RISC-V has also been studied as a target for return-oriented programming (ROP). One cited paper reports that RISC-V ROP can perform Turing-complete computation and arbitrary function calls using gadgets found in a version of GNU libc, and demonstrates a compiler that converts code in a Turing-complete language into RISC-V ROP chains. [citation: RISC-V ROP]
Evidence limitations
The supplied evidence supports RISC-V's identity as a free and open ISA, its definition by RISC-V International, its modularity, selected RV32I/RV64I and compressed-instruction behavior in a verification example, and its use in verification and security research. It does not provide detailed architectural specifications such as full instruction encodings, privilege modes, memory-model details, extension ratification status, or standard version history, so those topics are not expanded here.