RISC-V International

Organization

RISC-V International is the organization formed in 2015 to further the standardization and adoption of the RISC-V instruction set architecture. The available evidence places it in a rapidly growing, open, modular RISC-V ecosystem where optional extensions and custom implementations increase flexibility but also create standardization and verification challenges.

First seen 5/27/2026

Last seen 5/28/2026

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Overview

RISC-V International is identified in the available evidence as the organization formed in 2015 to further the standardization and adoption of the RISC-V instruction set architecture (ISA). The same source describes the RISC-V project as originating at the University of California, Berkeley in 2010, with the first RISC-V specifications made public in 2011. [C1]

The organization is situated in an ecosystem built around an open, royalty-free ISA. The evidence states that RISC-V is provided under royalty-free open-source licenses and that its architecture has been adopted across sectors, with companies developing processors and systems-on-chip based on RISC-V. [C2]

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NEIGHBORHOOD

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RELATIONSHIPS

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RISC-V mentions → 95% 1e

RISC-V International has announced several new extensions to the RISC-V ISA.

CITATIONS

9 sources

9 citations — click to expand

[1] RISC-V International was formed in 2015 to further standardization and adoption of the RISC-V ISA; the RISC-V project began at UC Berkeley in 2010 and initial specifications were public in 2011. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi

[2] RISC-V is described as being provided under royalty-free open-source licenses and adopted in processors and SoCs across sectors. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi

[3] RISC-V International is described as having more than 200 members, including Google, Qualcomm, NVIDIA, IBM, and Western Digital. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi

[4] RISC-V openness promotes collaboration and reuse of shared tools, and its modular and extensible architecture can be adapted to project needs. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi

[5] RISC-V has modular base parts and optional extensions; its base and extensions are developed collectively, and standard extensions are specified to work with standard bases and with one another. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi

[6] RISC-V International has announced several new extensions, and the RISC-V ISA encourages user-developed extensions and modifications. RISC-V Microarchitecture Verification Approaches

[7] RISC-V standardization and verification are identified as challenges when accommodating diverse extensions and implementations, with fragmentation prevention noted as important. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi

[8] RISC-V extension development can be faster than extension verification; verification challenges often involve microarchitecture and pipeline behavior rather than only instruction correctness. RISC-V Microarchitecture Verification Approaches

[9] The compressed instructions extension may reduce power consumption, code size, and memory use; RVGC combines a RISC-V base, G extensions, and the C extension for general-purpose OS support. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi