Ibex

CodeArtifact

Ibex is a small 32-bit RISC-V CPU core, previously known as zero-riscy, written in SystemVerilog and maintained by lowRISC. It has been used as a case-study implementation in several verification efforts, including the TestRIG randomized testing ecosystem with RVFI-DII instrumentation, automated simulation-based processor verification, and end-to-end power/leakage contract verification of masked cryptographic software.

First seen 5/27/2026

Last seen 6/26/2026

Evidence 6 chunks

Wiki v2

WIKI

Overview

Ibex is a small 32-bit RISC-V CPU core that was previously known as zero-riscy. It is developed as an open-source SystemVerilog implementation and is maintained in the lowRISC/ibex GitHub repository. [C1]

Architecture

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NEIGHBORHOOD

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RELATIONSHIPS

5 connections

TestRIG ← evaluates 95% 8e

TestRIG has been used to test the Ibex RISC-V processor.

RISC-V implements → 100% 5e

Ibex is a simple 32-bit RISC-V implementation.

RVFI-DII implements → 90% 2e

Ibex is instrumented with RVFI-DII for use in TestRIG.

RVFI-DII uses → 90% 2e

Ibex is instrumented with RVFI-DII to participate in the TestRIG ecosystem.

RISC-V targets ISA → 95% 1e

Ibex is a RISC-V core, indicating the code artifact targets/implements the RISC-V instruction set architecture.

LINKED ENTITIES

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RISC-V TARGETS_ISA Extracted graph relationship

CITATIONS

4 sources

4 citations — click to collapse

[1] Ibex is a small 32-bit RISC-V CPU core, previously known as zero-riscy, written in SystemVerilog. lowRISC/ibex GitHub repository

[2] Ibex is characterized as a simple 32-bit RISC-V implementation in the TestRIG paper, alongside Piccolo, and is instrumented with RVFI-DII under TestRIG requirements (8 MiB at 0x80000000, access faults elsewhere, reset to zeroed state). Randomized Testing of RISC-V CPUs using Direct Instruction Injection (TestRIG)

[3] Instrumenting Ibex with RVFI-DII required modifying its pipeline stages and resulted in a verification setup of more than 450 lines of code. Large-Scale RISC-V Processor Verification Using Automated...

[4] A power/leakage contract was written for the RISC-V Ibex core without modifying the hardware design, enabling end-to-end security verification between masked software and gate-level hardware. Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches