Ibex
CodeArtifactIbex is a simple 32-bit RISC-V implementation referenced in the TestRIG randomized testing ecosystem. The TestRIG paper lists Ibex among open processor implementations used with standardized RVFI-DII-based verification infrastructure.
First seen 5/27/2026
Last seen 6/8/2026
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Overview
Ibex is described in the TestRIG paper as one of several RISC-V CPU implementations considered in the TestRIG verification ecosystem. In that comparison, Ibex and Piccolo are characterized as simple 32-bit implementations, while other listed implementations include RVBS, Flute, and Toooba. The same passage provides an Ibex repository reference at https://github.com/CTSRD-CHERI/ibex. [C1]
Role in the TestRIG ecosystem
NEIGHBORHOOD
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4 connectionsTestRIG has been used to test the Ibex RISC-V processor.
Ibex is a simple 32-bit RISC-V implementation.
Ibex is instrumented with RVFI-DII for use in TestRIG.
Ibex is instrumented with RVFI-DII to participate in the TestRIG ecosystem.
LINKED ENTITIES
2 linksCITATIONS
3 sources3 citations — click to collapse
[1] C1: Ibex is listed among RISC-V CPU implementations in the TestRIG paper, and Ibex and Piccolo are described as simple 32-bit implementations; the paper footnote gives the Ibex repository URL. Randomized Testing of RISC-V CPUs using Direct
[2] C2: TestRIG participants must use RVFI-DII instrumentation and meet interface, memory, access-fault, and reset-state expectations. Randomized Testing of RISC-V CPUs using Direct
[3] C3: TestRIG collects compatible implementations and verification engines in an open-source repository and is presented as accelerating development toward standardized RISC-V testing. Randomized Testing of RISC-V CPUs using Direct