Skip to content
STIMSMITH

Ibex

CodeArtifact WIKI v1 · 5/27/2026

Ibex is a simple 32-bit RISC-V implementation referenced in the TestRIG randomized testing ecosystem. The TestRIG paper lists Ibex among open processor implementations used with standardized RVFI-DII-based verification infrastructure.

Overview

Ibex is described in the TestRIG paper as one of several RISC-V CPU implementations considered in the TestRIG verification ecosystem. In that comparison, Ibex and Piccolo are characterized as simple 32-bit implementations, while other listed implementations include RVBS, Flute, and Toooba. The same passage provides an Ibex repository reference at https://github.com/CTSRD-CHERI/ibex. [C1]

Role in the TestRIG ecosystem

TestRIG proposes a standardized communication interface so that verification engines, models, and implementations can be interchangeable and improved independently. Ibex is listed among the implementations discussed in that ecosystem. [C1]

For implementations participating in TestRIG, the paper states that they must be extended with RVFI-DII instrumentation. TestRIG participants are expected to be architecturally identical, expose an RVFI-DII interface, provide 8 MiB of memory at address 0x80000000, return access faults for other addresses, and support reset to a known state including zeroed registers and zeroed memory. [C2]

Architecture scope

The available evidence identifies Ibex as a 32-bit implementation in the context of RISC-V CPU testing. It is therefore linked here as implementing RISC-V, but the evidence provided does not specify Ibex microarchitectural details beyond its simple 32-bit characterization. [C1]

Related verification context

The TestRIG paper describes TestRIG as an open-source repository collecting TestRIG-compatible implementations and verification engines. It also states that TestRIG accelerates development by providing a tighter debugging loop and aims to support a standardized testing framework for RISC-V based on instrumented open implementations. [C3]

LINKED ENTITIES

2 links
TestRIG EVALUATES
RISC-V IMPLEMENTS

CITATIONS

3 sources
3 citations
[1] C1: Ibex is listed among RISC-V CPU implementations in the TestRIG paper, and Ibex and Piccolo are described as simple 32-bit implementations; the paper footnote gives the Ibex repository URL. Randomized Testing of RISC-V CPUs using Direct
[2] C2: TestRIG participants must use RVFI-DII instrumentation and meet interface, memory, access-fault, and reset-state expectations. Randomized Testing of RISC-V CPUs using Direct
[3] C3: TestRIG collects compatible implementations and verification engines in an open-source repository and is presented as accelerating development toward standardized RISC-V testing. Randomized Testing of RISC-V CPUs using Direct