Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches
PaperFirst seen 6/26/2026
Last seen 6/26/2026
Evidence 8 chunks
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20 connectionsThey propose a tighter model accounting for glitch propagation termination and formally develop it.
They verify software compliance under t-probing and prove end-to-end t-probing security.
They present the first end-to-end verification tool for transient/glitch-aware leakage contracts and link to the repository.
Affiliation line in the paper header.
IAIK appears in the affiliation email domain.
They apply their approach to a RISC-V core.
Case study uses the Ibex processor to demonstrate the method.
Text mentions RV32I as a configuration relevant to the model.
They reuse the 2-safety approach to encode hardware compliance properties.
Symbolic execution is applied to the contract to produce leak sequences.
Context establishes masking as the countermeasure whose security is being verified end-to-end.
Transition leakage is explicitly defined and incorporated into the combined model.
They formalize and incorporate glitch effects into their leakage model.
Discussion contrasts their methodology and limitations of Genoa-based flow.
Mentions reliance on scVerif in prior leakage contract verification.
Survey of related verification tools includes MaskVerif.
Author listing in the paper header.
Contrasts Coco’s comprehensive but expensive approach with modular leakage contracts.
Author listing in the paper header.
Author listing in the paper header.