Symbolic Execution

Technique

Symbolic execution is identified in the provided evidence as a formal-methods technique used for test-case generation at the instruction-set-simulator level in processor verification workflows.

First seen 5/25/2026

Last seen 6/7/2026

Evidence 5 chunks

Wiki v1

WIKI

Overview

In the supplied evidence, symbolic execution appears as a formal-methods technique used in processor-verification research. Specifically, formal methods based on symbolic execution techniques have been used for test-case generation at the instruction-set simulator (ISS) level.^[1]

Role in processor verification

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NEIGHBORHOOD

1 nodes · 0 edges

graph · Symbolic Execution · depth=1

RELATIONSHIPS

4 connections

Examiner ← uses 100% 2e

Examiner uses symbolic execution on ARM ASL code to generate test cases.

ARM Architecture Specification Language (ASL) implements → 100% 2e

The paper implements the first symbolic execution engine for ARM ASL to generate test cases.

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← compares with 75% 1e

The paper mentions symbolic execution as a related approach

path explosion in symbolic execution ← part of 90% 1e

Path explosion is a known challenge in symbolic execution, but is not an issue in this context due to limited ASL constraints.

LINKED ENTITIES

1 links

Processor Verification USED_FOR Extracted graph relationship

CITATIONS

2 sources

2 citations — click to collapse

[1] Symbolic-execution-based formal methods have been used for test-case generation at the ISS level. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[2] The cited evidence discusses symbolic execution in the broader context of processor verification techniques. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing