FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution
PaperFirst seen 6/20/2026
Last seen 6/20/2026
Evidence 10 chunks
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26 connectionsThe FuSS paper evaluates the framework on VeeRwolf.
The FuSS paper evaluates the framework on CVA6.
The paper compares FuSS against traditional random test generation as a baseline.
The paper compares FuSS with property checking based fuzzing approaches.
The paper uses DifuzzRTL as both a baseline and as the underlying fuzzer engine.
The paper introduces the FuSS hardware fuzzing framework that combines coverage-guided fuzzing with selective symbolic execution.
The FuSS paper evaluates the framework on PicoSoC.
The FuSS paper evaluates the framework on UeRVSoC.
The paper mentions PSOFuzz as a related hardware fuzzing approach.
The paper is authored by Aruna Jayasena.
The paper is authored by Sai Suprabhanu Nallapaneni.
The paper is authored by Prabhat Mishra.
All authors are affiliated with the University of Florida.
The paper mentions SoCFuzzer as a related hardware fuzzing approach for SoC security.
The paper uses EBMC for reproducing results related to fuzzing with property checking.
The paper uses Doob's Martingale analysis for its theoretical analysis of FuSS.
The paper uses the Azuma-Hoeffding inequality in its theoretical analysis.
The paper mentions ProcessorFuzz as a related hardware fuzzing approach.
The paper mentions MABFuzz as a related hardware fuzzing approach.
The paper mentions Cascade as a related hardware fuzzing approach.
The paper mentions SurgeFuzz as a related hardware fuzzing approach.
The paper mentions FormalFuzzer as a related work combining formal methods with fuzzing.
The paper mentions HyPFuzz as a related work combining formal verification with fuzzing.
The paper mentions TheHuzz as a related hardware fuzzing approach.
The paper mentions HD-Fuzz as a related hardware fuzzing approach.
The paper mentions ChatFuzz as a related hardware fuzzing approach.