FuSS Framework
ToolFirst seen 6/20/2026
Last seen 6/20/2026
Evidence 11 chunks
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20 connectionsFuSS generates and uses test vectors to achieve coverage goals.
The FuSS framework implements coverage-guided fuzzing as a core component.
The FuSS framework implements selective symbolic execution to overcome coverage plateaus.
The FuSS framework implements hardware fuzzing as its primary validation approach.
FuSS extracts source-destination pairs from the CFG to guide symbolic execution.
FuSS implements a plateau detection mechanism to decide when to invoke symbolic execution.
FuSS uses and updates a fuzzing corpus throughout its execution.
FuSS generates and uses assembly instruction sequences as test inputs for hardware designs.
FuSS evaluates its effectiveness using branch coverage as a metric.
FuSS evaluates its effectiveness using toggle coverage as a metric.
The paper introduces the FuSS hardware fuzzing framework that combines coverage-guided fuzzing with selective symbolic execution.
FuSS uses design instrumentation as the first step in its pipeline.
FuSS uses hardware-program context mapping to connect fuzzing trajectories to hardware states.
FuSS uses Verilator to convert hardware models into cycle-accurate software models.
FuSS uses angr for CFG generation and address decoding.
FuSS uses the Z3 SMT solver for constraint solving during symbolic execution.
FuSS uses a modified version of DifuzzRTL as its fuzzer engine.
FuSS uses the VEX intermediate representation via angr for symbolic execution.
FuSS uses cycle-accurate simulation via Verilator for hardware modeling.
FuSS implements a testbench that instantiates hardware description and controls clock and reset lines.