cycle-accurate simulation

Concept

Cycle-accurate simulation refers to modeling and executing hardware (or hardware-described systems) one clock cycle at a time, so that the simulator's behavior matches the target design's behavior on every cycle. It is widely used in processor modeling, high-level synthesis (HLS) validation, and in solver-aided hardware verification where properties must be reasoned about over many concrete cycles of execution.

First seen 6/9/2026

Last seen 6/9/2026

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WIKI

cycle-accurate simulation

Definition and purpose

Cycle-accurate simulation is the practice of constructing a software model of a digital system whose state advances one clock cycle at a time, in lockstep with the design under study. Such simulators are used both for early hardware/software co-design, where detailed processor or accelerator models are needed before silicon exists, and for verification, where one must reason about the exact sequence of states a circuit visits.

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NEIGHBORHOOD

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graph · cycle-accurate simulation · depth=1

LINKED ENTITIES

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rtlv performs_cycle-accurate_symbolic_execution_for_verification The rtlv paper explicitly frames the tool as enabling 'cycle-accurate reasoning about software running on the hardware' through cycle-by-cycle symbolic execution.

SymbiYosys alternative_approach_using_unrolled_transition_relations The rtlv paper discusses SymbiYosys as a verification tool that scales poorly for many-cycle, cycle-accurate reasoning compared to rtlv.

Rosette solver-aided_programming_language_used_for_cycle-accurate_symbolic_execution The rtlv paper describes Rosette's hybrid symbolic execution with type-driven state merging and rewrite rules as features that enable cycle-accurate verification.

CITATIONS

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13 citations — click to expand

[1] Cycle-accurate simulators are essential for modern hardware and software design, and detailed processor modeling is challenging. Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation

[2] The Reduced Colored Petri Net (RCPN) model provides an intuitive mirror of the processor pipeline block diagram and can generate high-performance cycle-accurate simulators without the exponential complexity of standard Colored Petri Nets. Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation

[3] RCPN-generated cycle-accurate simulators for XScale and StrongArm achieved ~15x speedup over the SimpleScalar ARM simulator. Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation

[4] A large semantic gap between HLS design and low-level (on-board or RTL) simulation makes FPGA-targeted design hard for non-experts, and low-level simulation can be very slow. Rapid Cycle-Accurate Simulator for High-Level Synthesis

[5] Existing commercial FPGA HLS software simulators can sometimes produce incorrect results, motivating an alternative cycle-accurate simulation flow. Rapid Cycle-Accurate Simulator for High-Level Synthesis

[6] FLASH extracts scheduling information from the HLS tool and automatically constructs an equivalent cycle-accurate simulation model while preserving C semantics. Rapid Cycle-Accurate Simulator for High-Level Synthesis

[7] FLASH runs three orders of magnitude faster than RTL simulation. Rapid Cycle-Accurate Simulator for High-Level Synthesis

[8] SMT-based tools such as SymbiYosys verify cycle-stepped properties by unrolling the circuit's transition relation into a long chain of T(s_i, s_{i+1}) constraints. rtlv: push-button verification of software on hardware

[9] SMT solvers exhibit poor performance when reasoning about long chains of unrolled transitions, especially when the circuit state is largely symbolic. rtlv: push-button verification of software on hardware

[10] rtlv transforms the transition relation into an imperative step function and symbolically executes the circuit cycle by cycle, enabling efficient cycle-accurate reasoning about software on hardware. rtlv: push-button verification of software on hardware

[11] rtlv leverages Rosette's hybrid symbolic execution with type-driven state merging and rewrite rules to simplify symbolic expressions at control-flow joins, avoiding path explosion. rtlv: push-button verification of software on hardware

[12] Verifying that boot code clears all microarchitectural state in a PicoRV32 CPU requires modeling 104 cycles of execution. rtlv: push-button verification of software on hardware

[13] SymbiYosys did not finish verifying the 104-cycle PicoRV32 boot-clearing property within 12 hours, while rtlv completes the same verification in about 1.3 seconds. rtlv: push-button verification of software on hardware