Assembly Instruction Sequence
ConceptAn ordered series of assembly instructions (opcodes and operands) supplied to a hardware testbench as a program input, used as a test vector in hardware fuzzing frameworks such as FuSS.
First seen 6/20/2026
Last seen 6/20/2026
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Assembly Instruction Sequence
An assembly instruction sequence is an ordered collection of assembly instructions, each composed of an opcode and one or more operands, supplied as a program input to a hardware design under verification (DUV). In the context of hardware verification and fuzzing, instruction sequences serve as test vectors that drive the hardware through specific execution paths.
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1 connectionsFuSS generates and uses assembly instruction sequences as test inputs for hardware designs.
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[1] An assembly instruction sequence is represented as a byte (8-bit) array with internal segments separating individual instructions. FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution
[2] Each instruction consists of an opcode and one or more operands. FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution
[3] The fuzzer generates assembly instruction sequences A_f as test programs simulated against the hardware design. FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution
[4] Selective symbolic execution generates a new instruction sequence A_s to bridge from source s_i to destination d_i on the hardware CFG. FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution
[5] The final program A_{f+s} is constructed by concatenating the fuzzer-generated prefix with the symbolic execution-generated suffix. FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution
[6] Assembly instruction sequences serve as input to neural instruction embedding models such as BinBert for binary code understanding. BinBert: Binary Code Understanding with a Fine-tunable and Execution-aware Transformer