Test Vector
ConceptIn the cited processor-verification fuzzing flow, a test vector is a fuzzer-generated, bounded input that is used as an instruction stream for co-simulation of an RTL processor core against a reference ISS. A Translation Buffer deterministically expands the bounded test vector into an endless instruction stream, while execution control, mutation strategies, and post-processing manage runtime, coverage growth, mismatch detection, and duplicate bug reports.
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Definition
In the cited cross-level processor-verification approach, a test vector is the input generated by a coverage-guided fuzzer and used as the instruction stream for co-simulation. The co-simulation combines an RTL core under test with a reference instruction-set simulator (ISS), and both execute the instruction stream derived from the test vector. [test-vector-role]
Representation as an instruction stream
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