Scalable Formal Verification Strategies for RISC-V Based Control Paths: A Review

Paper

First seen 7/16/2026

Last seen 7/16/2026

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34 connections

Comparative Evaluation of Open-Source Formal Tools for RISC-V Processor Verification mentions → 97% 2e

The review paper discusses the comparative evaluation of open-source tools, citing Fernandez et al. (2024).

Scalability of Formal Verification in Multi-Core RISC-V Systems mentions → 97% 2e

The review paper discusses the scalability study on multi-core RISC-V systems, citing Keller and Matsuda (2024).

Coq uses → 90% 2e

The review discusses Coq-based frameworks for ISA-level verification as foundational to scalable RISC-V verification.

RISC-V Formal: A Framework for Formal Specification and Verification of RISC-V ISA mentions → 97% 2e

The review paper summarizes and cites the RISC-V Formal paper.

Symbiotic Verification of RISC-V Processors mentions → 97% 2e

The review paper summarizes and cites the Symbiotic Verification paper.

Deep Inference of RTL Assertions Using Transformer Models mentions → 93% 2e

The review cites the Deep Inference paper as a reference for assertion inference from RTL using transformer models.

Open-Source Hardware mentions → 90% 1e

The paper discusses open-source hardware ecosystems and the importance of scalable verification for them.

System On Chip mentions → 90% 1e

The paper mentions SoC verification as a challenge for scalability.

Compositional Reasoning uses → 90% 1e

The paper discusses compositional reasoning as a technique to address scalability in RISC-V verification.

abstraction refinement uses → 90% 1e

The review recommends abstraction refinement as a key technique for scalable RISC-V verification.

Predicate Abstraction uses → 88% 1e

The review recommends predicate abstraction specific to RISC-V semantics as a future direction.

Reinforcement Learning for Proof Generation uses → 87% 1e

The review suggests reinforcement learning for generating proof hints and automatic solver heuristics as future directions.

Non-Interference and Information Flow Analysis uses → 88% 1e

The review discusses non-interference and information flow analysis for security verification in RISC-V control paths.

Secure Boot Verification mentions → 88% 1e

The review mentions secure boot verification as an important topic in high-assurance security verification for RISC-V.

Neuromorphic and Quantum Control Paths mentions → 90% 1e

The review discusses formal verification for quantum and neuromorphic controllers as an emerging challenge.

Abstract Interpretation uses → 88% 1e

The review recommends abstract interpretation tools to be integrated into standard EDA flows for RISC-V verification.

PicoRV32 evaluates → 92% 1e

The review reports experimental results using PicoRV32 as one of the open-source RISC-V processor cores in comparisons.

Rocket Core evaluates → 92% 1e

The review reports experimental results using Rocket Core as one of the open-source RISC-V processor cores in comparisons.

Ariane evaluates → 92% 1e

The review reports experimental results using Ariane as one of the open-source RISC-V processor cores in comparisons.

Floating Point Unit evaluates → 88% 1e

The review reports benchmark experiments that changed RISC-V cores with floating-point unit and custom extension logic to see how well parametric invariants handle design variations.

RV-Match: A Formal RISC-V Instruction-Level Semantics Matcher mentions → 95% 1e

The review paper summarizes the RV-Match paper and its contributions to formal RISC-V instruction semantics matching.

SMT-based Bounded Model Checking for RISC-V Control Logic mentions → 95% 1e

The review paper summarizes the SMT-based Bounded Model Checking paper.

CSRFormal: Formal Verification of Control and Status Registers in RISC-V mentions → 95% 1e

The review paper summarizes the CSRFormal paper on verifying RISC-V control and status registers.

R2V: A RISC-V to Verilog Translation Framework for Formal Verification mentions → 95% 1e

The review paper summarizes the R2V paper on translating RISC-V to Verilog for formal verification.

Hybrid Automata and Formal Modeling for Safety-Critical RISC-V Control Systems mentions → 95% 1e

The review paper summarizes the Hybrid Automata paper on safety-critical RISC-V control systems.

Isabelle uses → 85% 1e

The review recommends a unified open-source verification stack including Isabelle for RISC-V formal verification.

JasperGold uses → 85% 1e

The review mentions JasperGold as part of the current RISC-V formal verification toolchain.

Aparna Mohan authored by → 100% 1e

The review paper is authored by Aparna Mohan from North Carolina State University.

SymbiYosys uses → 87% 1e

The review mentions SymbiYosys as part of the current RISC-V formal verification toolchain.

North Carolina State University authored by → 100% 1e

The paper is affiliated with North Carolina State University.

Symbolic Execution uses → 95% 1e

The review covers symbolic execution as one of the scalable formal verification approaches for RISC-V control logic.

Bounded Model Checking uses → 95% 1e

The review covers bounded model checking as one of the scalable formal verification approaches for RISC-V control logic.

AI-Assisted Verification uses → 95% 1e

The review covers AI-assisted theorem proving as one of the scalable formal verification approaches.

Parameterised Invariants uses → 90% 1e

The review covers invariant-based methods as one of the scalable formal verification approaches.