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Scalability of Formal Verification in Multi-Core RISC-V Systems

Paper
First seen 7/16/2026
Last seen 7/16/2026
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Scalable Formal Verification Strategies for RISC-V Based Control Paths: A Review ← mentions 97% 2e
The review paper discusses the scalability study on multi-core RISC-V systems, citing Keller and Matsuda (2024).
Multi-Core RISC-V Systems evaluates → 98% 1e
The paper looks at how long it takes to do formal verification on multi-core RISC-V systems with shared control logic and memory controllers.
SMT-based Verification uses → 92% 1e
The paper uses SMT+BMC for verifying multi-core RISC-V systems.
AI-Assisted Verification uses → 90% 1e
The paper uses AI-assisted Coq for verifying 4-core RISC-V systems.