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STIMSMITH

SMT-based Bounded Model Checking for RISC-V Control Logic

Paper
First seen 7/16/2026
Last seen 7/16/2026
Evidence 2 chunks

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RELATIONSHIPS

5 connections
SMT-based Verification uses → 98% 1e
The paper applies SMT solvers to verify bounded executions of RISC-V control logic.
Bounded Model Checking uses → 98% 1e
The paper applies bounded model checking to verify RISC-V control logic.
SMT Solvers uses → 97% 1e
The paper uses SMT solvers to verify bounded executions of RISC-V control logic.
Finite State Machine evaluates → 92% 1e
The paper provided efficient bug detection on finite traces in RISC-V ALUs and control FSMs.
Scalable Formal Verification Strategies for RISC-V Based Control Paths: A Review ← mentions 95% 1e
The review paper summarizes the SMT-based Bounded Model Checking paper.