Finite State Machine
ConceptA finite state machine (FSM) is a computational model that transitions among a finite set of states in response to inputs or events. FSMs are widely used to model digital hardware, communication protocols, processors, pipeline stages, FPGA control logic, and even specification languages for software testing. The model underpins techniques such as Interval Property Checking (IPC), CSR-transition coverage in processor fuzzing, and synchronization handshakes in SoC bus protocols.
First seen 5/26/2026
Last seen 7/16/2026
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Overview
A finite state machine (FSM) is a computational model that transitions among a finite set of states in response to inputs or events. FSMs are widely used to model digital hardware, communication protocols, processors, and other discrete-state systems. [C1][C2][C3]
Formal FSM model in hardware verification
NEIGHBORHOOD
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17 connectionsRegister coverage aims to track FSM states in the processor by monitoring register values.
IPC models synchronous circuits as finite state machines.
CSR-transition coverage tracks processor FSM state transitions through CSR changes.
Privilege mode is part of the processor FSM state tracked by CSR transitions.
Control FSMs are the primary targets of control path verification in RISC-V processors.
ProcessorFuzz aims to explore different FSM states of the processor.
FSMs are described in RTL hardware description languages.
DIFUZZRTL monitors FSM state transitions via register coverage.
CSR-transition coverage tracks FSM state transitions in the processor via CSR changes.
The Ibex Core controller uses a Finite State Machine to manage execution.
The next state function is a component of the finite state machine model.
The FSM model uses a next state function to define transitions.
TheHuzz uses FSM coverage among other metrics
Multicycle instructions use an FSM in an early pipeline stage for dispatching.
Finite state machine synchronization requirements create hard-to-activate regions.
The paper provided efficient bug detection on finite traces in RISC-V ALUs and control FSMs.
The specification language incorporates finite state machines to model system behavior.
LINKED ENTITIES
8 linksspecification language USES Extracted graph relationship
Interval Property Checking USES The previous article already established IPC as a technique that unrolls the FSM transition relation; preserved and re-cited.
Data Path Modeling USES Mapping functions Data_R and Valid_R use the FSM state s as input to model pipeline datapath; preserved from previous article.
register coverage USES DIFUZZRTL monitors datapath registers to infer the current FSM state; preserved from previous article.
CSR-transition coverage USES ProcessorFuzz monitors CSR transitions to expose processor FSM state; preserved from previous article.
DiFuzzRTL USES Tool that uses register coverage to infer FSM state in processor fuzzing; preserved from previous article.
ProcessorFuzz USES Tool proposing CSR-transition coverage and the Transition Unit workflow; preserved from previous article.
TheHuzz USES Instruction-fuzzing tool that tags certain processor bugs as FSM-component bugs (e.g., mor1kx cache controller).
CITATIONS
15 sources15 citations — click to expand
[1] FSMs are computational models that transition among a finite set of states in response to inputs, used for hardware, protocols, and discrete-state systems. Reachability problems for communicating finite state machines
[2] An FSM overlay on FPGAs uses memory decomposition on transitional logic and achieves 15-29% LUT reduction per FSM and 77-99% LUT reduction across different FSMs. A Scalable, Low-Overhead Finite-State Machine Overlay for Rapid FPGA Application Development
[3] A synchronous circuit is modeled as the FSM M = (I, S, S0, Δ, Λ, O) with transition relation T(s, s') = ∃x ∈ B^n : s' ≡ Δ(x, s). Reachability problems for communicating finite state machines
[4] Interval Property Checking unrolls the FSM transition relation T over [0, c] and conjoins it with [[f]]_t to search for counterexamples via SAT. Reachability problems for communicating finite state machines
[5] Mapping functions Data_R(s, i) and Valid_R(s, i) capture architectural register values across pipeline stages, gated by a forwarding FSM in an early pipeline stage. Reachability problems for communicating finite state machines
[6] A processor is described as a complex FSM, with CSRs exposing the current state and transitions in CSRs signifying a new FSM state. Reachability problems for communicating finite state machines
[7] DIFUZZRTL's register coverage monitors datapath registers to infer current FSM state, but only tracks current state and can miss transitions whose previous state matters. A Scalable, Low-Overhead Finite-State Machine Overlay for Rapid FPGA Application Development
[8] A Bug 2 RISC-V case shows that when a transition P1 from N1 to N2 has both endpoints covered individually, current-state coverage fails to drive P1 and the bug is missed. A Scalable, Low-Overhead Finite-State Machine Overlay for Rapid FPGA Application Development
[9] ProcessorFuzz proposes CSR-transition coverage analogous to edge coverage in software fuzzing, with selection criteria on status and configuration CSRs. A Scalable, Low-Overhead Finite-State Machine Overlay for Rapid FPGA Application Development
[10] ProcessorFuzz's transition map stores (Im, S0, S1) tuples, with Im included because different instructions can produce the same CSR-value transition (e.g., fflags from FP div/sqrt). A Scalable, Low-Overhead Finite-State Machine Overlay for Rapid FPGA Application Development
[11] Communicating FSMs over unbounded FIFO channels make reachability undecidable in general but decidable for the recognizable channel property; the rational channel case is open. Reachability problems for communicating finite state machines
[12] FuSS models SoC hardware designs as FSMs; the AXI-4 Lite write transaction uses two synchronized FSMs (master, slave) coordinating through awvalid/awready/wvalid/wready/bvalid/bready handshakes across IDLE, ADDR/ADDR_READY, WRITE/WR_READY, RESPOND, and DONE states. FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution
[13] In SoC hardware fuzzing, the complex interactions between multiple FSMs coupled with rare conditional dependencies create hard-to-activate regions and coverage plateaus. FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution
[14] TheHuzz classifies certain processor bugs as FSM-component bugs, e.g., mor1kx Bug B4 'Failure to detect cache coherency violation' is tagged as FSM in the cache controller (CWE-1202). TheHuzz: Instruction Fuzzing of Processors Using Golden Reference Models
[15] A contract-oriented specification language is extended with finite state machines to support symbolic animation and full test-scenario generation, including arbitrary-type CSP domains and a string type builder. A Constraint Logic Programming Approach to Automated Testing