privilege mode

Concept

In the provided RISC-V evidence, privilege mode is the processor privilege level used to qualify operations such as memory access, virtual-memory loads, trap handling, interrupt state, and access to performance counters. ProcessorFuzz treats privilege-related CSR transitions as verification-relevant behavior, and its reported Dromajo bug shows that using the wrong effective privilege mode for page-table accesses and PMP checks can violate the RISC-V privileged specification.

First seen 5/26/2026

Last seen 6/8/2026

Evidence 12 chunks

Wiki v3

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privilege mode

Definition

In the provided evidence, privilege mode is a RISC-V execution privilege level used by architectural mechanisms such as status CSRs, memory-access controls, virtual-memory behavior, interrupt state, and trap handling. The evidence names machine, supervisor, and user privilege levels through mstatus fields parameterized by x = {M, S, U}.

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NEIGHBORHOOD

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RELATIONSHIPS

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riscv_instr_gen_config ← implements 90% 2e

riscv_instr_gen_config configures the privilege mode supported by the test.

ProcessorFuzz ← mentions 90% 2e

ProcessorFuzz tracks privilege mode transitions as part of CSR-transition coverage.

Finite State Machine part of → 85% 2e

Privilege mode is part of the processor FSM state tracked by CSR transitions.

Control and Status Registers part of → 85% 2e

Privilege mode status is tracked through CSR fields like mstatus.xPP.

mstatus CSR ← part of 90% 1e

mstatus CSR holds previous privilege mode and controls memory operations privilege.

LINKED ENTITIES

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mstatus CSR PART_OF Extracted graph relationship

CITATIONS

6 sources

6 citations — click to expand

[1] Privilege mode in the evidence includes machine, supervisor, and user levels, expressed by mstatus fields parameterized as x = {M, S, U}. ProcessorFuzz: Processor Fuzzing with Control and

[2] mstatus fields record or control privilege-mode behavior for interrupt state, previous privilege mode before traps, memory-operation privilege, supervisor access to user memory, virtual-memory load privilege, WFI execution privilege, and SRET trap behavior. ProcessorFuzz: Processor Fuzzing with Control and

[3] Other privileged CSRs selected by ProcessorFuzz include trap-cause CSRs for machine or supervisor traps, medeleg for delegating exceptions from machine mode to supervisor mode, and counter-enable CSRs controlling counter availability for supervisor or user mode. ProcessorFuzz: Processor Fuzzing with Control and

[4] ProcessorFuzz uses CSR-transition coverage to detect inputs that increase coverage, and its RISC-V CSR selection includes both privileged and unprivileged CSR groups. ProcessorFuzz: Processor Fuzzing with Control and

[5] ProcessorFuzz reported a Dromajo bug where implicit page-table accesses should have used supervisor mode but were observed at user-mode privilege level while executing user-mode programs. ProcessorFuzz: Processor Fuzzing with Control and

[6] The Dromajo analysis also found PMP checks performed in user mode when no PMP entries were set, which the paper describes as violating the RISC-V privileged specification in two counts. ProcessorFuzz: Processor Fuzzing with Control and