riscv_instr_gen_config

CodeArtifact

riscv_instr_gen_config is a riscv-dv configuration class randomized by riscv_instr_base_test.sv to control key parameters for generated RISC-V assembly tests, including ISA extensions, supported privilege mode, main/subprogram instruction counts, and whether specific instruction classes such as ebreak, dret, fence, and wfi are suppressed.

First seen 5/26/2026

Last seen 5/28/2026

Evidence 1 chunks

Wiki v1

WIKI

riscv_instr_gen_config

riscv_instr_gen_config is a configuration class in the CHIPS Alliance open-source riscv-dv random instruction generator flow for RISC-V processor verification. It is randomized from the riscv_instr_base_test.sv test before assembly-program generation begins. The resulting configuration determines major constraints and switches used by the generated RISC-V assembly test program. [C1]

Role in the generation flow

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RELATIONSHIPS

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riscv_instr_base_test ← uses 100% 2e

riscv_instr_base_test randomizes riscv_instr_gen_config to configure the test.

privilege mode implements → 90% 2e

riscv_instr_gen_config configures the privilege mode supported by the test.

riscv-dv part of → 95% 2e

riscv_instr_gen_config is a configuration class within riscv-dv.

LINKED ENTITIES

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riscv_asm_program_gen USES Extracted graph relationship

CITATIONS

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[1] riscv_instr_gen_config is randomized from riscv_instr_base_test.sv and controls ISA extension selection, privilege mode, instruction counts, and suppression switches such as no_ebreak, no_dret, no_fence, and no_wfi. RISC-V source class riscv_asm_program_gen, the brain behind ...

[2] riscv_asm_program_gen generates complete RISC-V assembly programs with sections such as initialization, instruction, data, stack, page table, interrupt, and exception handling. RISC-V source class riscv_asm_program_gen, the brain behind ...