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riscv_instr_gen_config

CodeArtifact WIKI v1 · 5/26/2026

riscv_instr_gen_config is a riscv-dv configuration class randomized by riscv_instr_base_test.sv to control key parameters for generated RISC-V assembly tests, including ISA extensions, supported privilege mode, main/subprogram instruction counts, and whether specific instruction classes such as ebreak, dret, fence, and wfi are suppressed.

riscv_instr_gen_config

riscv_instr_gen_config is a configuration class in the CHIPS Alliance open-source riscv-dv random instruction generator flow for RISC-V processor verification. It is randomized from the riscv_instr_base_test.sv test before assembly-program generation begins. The resulting configuration determines major constraints and switches used by the generated RISC-V assembly test program. [C1]

Role in the generation flow

The evidence describes riscv_instr_gen_config as the first configuration object randomized before the riscv_asm_program_gen flow generates the assembly program. This places it upstream of the assembly-program construction process, where riscv_asm_program_gen later creates sections such as initialization, instruction, data, stack, page-table, interrupt, and exception-handling sections. [C1] [C2]

Configuration responsibilities

Randomization of riscv_instr_gen_config decides several test-generation properties: [C1]

  • The RISC-V extension set used for the generated program.
  • The supported privilege mode.
  • The instruction count in the main program.
  • The instruction count in subprograms.
  • Whether break instructions are generated, controlled through no_ebreak.
  • Similar suppression controls for no_dret, no_fence, and no_wfi.
  • Other Boolean-style variables that may be set according to DUT features and testbench stimulus-generation requirements.

Relationship to riscv_asm_program_gen

riscv_asm_program_gen is the assembly-program generator class that emits the complete RISC-V assembly program used to verify RISC-V IP. The configuration established by riscv_instr_gen_config precedes that generation and controls important aspects of what the program may contain. After configuration, riscv_asm_program_gen performs program construction through functions such as gen_program(), gen_program_header(), init_gpr(), directed instruction stream generation, main-program instruction-stream conversion, optional subprogram insertion, and host-interface section emission. [C1] [C2]

Practical significance

Because riscv_instr_gen_config encodes DUT- and testbench-dependent choices, it is the point where a verification environment can constrain generated stimulus to match the target RISC-V IP capabilities. For example, a DUT or testbench that should not receive certain instruction types can use variables such as no_ebreak, no_dret, no_fence, or no_wfi to prevent those instructions from being generated. [C1]

LINKED ENTITIES

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riscv_asm_program_gen USES

CITATIONS

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2 citations
[1] riscv_instr_gen_config is randomized from riscv_instr_base_test.sv and controls ISA extension selection, privilege mode, instruction counts, and suppression switches such as no_ebreak, no_dret, no_fence, and no_wfi. RISC-V source class riscv_asm_program_gen, the brain behind ...
[2] riscv_asm_program_gen generates complete RISC-V assembly programs with sections such as initialization, instruction, data, stack, page table, interrupt, and exception handling. RISC-V source class riscv_asm_program_gen, the brain behind ...