riscv_asm_program_gen
CodeArtifactriscv_asm_program_gen is a SystemVerilog/UVM class in the riscv-dv random instruction generator that builds complete RISC-V assembly programs for processor IP verification. Its gen_program() flow composes program sections, initializes GPRs, inserts directed and randomized instruction streams, handles subprograms, and adds host-interface and trap-handling support.
First seen 5/26/2026
Last seen 5/28/2026
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Overview
riscv_asm_program_gen is described as the class behind complete RISC-V assembly-program generation in the open-source riscv-dv random instruction generator used for RISC-V processor verification. The generated random test can be run with a design IP, and the class can address customization of RISC-V GPRs or instructions. [C1]
The class generates multiple sections of an assembly program, including initialization, instruction, data, stack, page-table, interrupt-handling, and exception-handling sections. [C2]
NEIGHBORHOOD
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15 connectionsgen_section is a function within riscv_asm_program_gen used to insert instruction sections.
gen_program_header is a function within riscv_asm_program_gen called by gen_program.
init_gpr is a function within riscv_asm_program_gen for initializing general purpose registers.
generate_directed_instr_stream is a function within riscv_asm_program_gen for inserting directed instruction streams.
insert_sub_program is a function within riscv_asm_program_gen for inserting sub-programs.
push_gpr_to_kernel_stack is a function within riscv_asm_program_gen for pushing GPRs to stack for trap handling.
riscv_asm_program_gen generates interrupt and exception handling sections in the assembly program.
riscv_asm_program_gen is the main class responsible for generating complete RISC-V assembly programs.
add_directed_instr_stream is a function within riscv_asm_program_gen called by gen_program.
riscv_asm_program_gen is a core class within riscv-dv.
gen_program is the main function defined in the riscv_asm_program_gen class.
get_directed_instr_stream is a function within riscv_asm_program_gen called by gen_program.
riscv_asm_program_gen generates the page table section of the assembly program.
riscv_asm_program_gen generates programs used for RTL verification of RISC-V IP.
riscv_asm_program_gen uses riscv_instruction_sequence to generate the full assembly program.
LINKED ENTITIES
1 linksCITATIONS
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[1] C1: riscv_asm_program_gen is a class in the open-source riscv-dv random instruction generator that generates complete RISC-V assembly programs for RISC-V IP verification and supports customization of RISC-V GPRs or instructions. RISC-V source class riscv_asm_program_gen, the brain behind ...
[2] C2: riscv_asm_program_gen generates assembly-program sections such as initialization, instruction, data, stack, page table, interrupt handling, and exception handling. RISC-V source class riscv_asm_program_gen, the brain behind ...
[3] C3: riscv_instr_gen_config is randomized from riscv_instr_base_test.sv and decides the extension, privilege mode, main and subprogram instruction counts, and flags such as no_ebreak, no_dret, no_fence, and no_wfi. RISC-V source class riscv_asm_program_gen, the brain behind ...
[4] C4: gen_program() is the main function that generates all sections of the program and calls other riscv_asm_program_gen functions sequentially. RISC-V source class riscv_asm_program_gen, the brain behind ...
[5] C5: gen_program() calls get_directed_instr_stream() and uses add_directed_instr_stream() to select directed-instruction generation ratios. RISC-V source class riscv_asm_program_gen, the brain behind ...
[6] C6: gen_program() calls gen_program_header(), which fills instr_stream with header content such as .include "user_init.s". RISC-V source class riscv_asm_program_gen, the brain behind ...
[7] C7: gen_program_header() calls gen_section("_start", str), inserting header instructions into instr_stream. RISC-V source class riscv_asm_program_gen, the brain behind ...
[8] C8: init_gpr() initializes general-purpose registers with random values. RISC-V source class riscv_asm_program_gen, the brain behind ...
[9] C9: generate_directed_instr_stream() decides ratios, inserts directed instruction streams, randomizes instructions, and selects rs1, rs2, and rd based on instruction type. RISC-V source class riscv_asm_program_gen, the brain behind ...
[10] C10: riscv_instr_sequence.generate_instr_stream() uses convert2asm() after the instruction stream is available. RISC-V source class riscv_asm_program_gen, the brain behind ...
[11] C11: main_program[hart].generate_instr_stream() is called from riscv_asm_program_gen to convert the instruction stream to string format. RISC-V source class riscv_asm_program_gen, the brain behind ...
[12] C12: insert_sub_program(sub_program[hart], instr_stream) is called when subprogram instructions are generated. RISC-V source class riscv_asm_program_gen, the brain behind ...
[13] C13: After main and subprogram generation, host-interface instructions are added through gen_section, including write_tohost, sw gp, tohost, t1, and _exit. RISC-V source class riscv_asm_program_gen, the brain behind ...
[14] C14: push_gpr_to_kernel_stack() pushes GPRs to the stack for trap handling, and gen_section() selects an mtvec_handler string containing exception and interrupt handlers. RISC-V source class riscv_asm_program_gen, the brain behind ...
[15] C15: If illegal-instruction or HINT-instruction ratios are zero, illegal or HINT instructions are not generated. RISC-V source class riscv_asm_program_gen, the brain behind ...
[16] C16: gen_program(), helper functions, riscv_instruction_sequence, base tests, and configuration helpers produce a complete RISC-V assembly program with randomized instructions and randomized GPR selections. RISC-V source class riscv_asm_program_gen, the brain behind ...
[17] C17: riscv_asm_program_gen is presented as a comprehensive utility in the riscv-dv verification ecosystem for automating RISC-V assembly-program generation with modular function calls and configuration support. RISC-V source class riscv_asm_program_gen, the brain behind ...