generate_directed_instr_stream

CodeArtifact

generate_directed_instr_stream() is a function in the riscv-dv assembly program generation flow. It is called during gen_program() after program header and GPR initialization steps, and it decides directed-instruction ratios, inserts directed instruction streams, and randomizes instruction operands such as rs1, rs2, and rd based on instruction type.

First seen 5/26/2026

Last seen 5/28/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

generate_directed_instr_stream() is part of the RISC-V assembly program generation flow described for the riscv_asm_program_gen class in the open-source CHIPS Alliance riscv-dv random instruction generator. The broader generator produces complete RISC-V assembly programs used for RISC-V IP verification, including initialization routines, instruction sections, data sections, stack sections, page tables, and interrupt/exception handling sections.

Role in the generation flow

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NEIGHBORHOOD

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RELATIONSHIPS

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riscv_asm_program_gen part of → 100% 2e

generate_directed_instr_stream is a function within riscv_asm_program_gen for inserting directed instruction streams.

directed instruction stream implements → 100% 2e

generate_directed_instr_stream implements the insertion and randomization of directed instruction streams.

gen_program ← uses 100% 2e

gen_program calls generate_directed_instr_stream to insert directed instruction streams.

LINKED ENTITIES

2 links

riscv_asm_program_gen member_of_generation_flow The evidence describes generate_directed_instr_stream() as a function called from the riscv_asm_program_gen program generation flow.

gen_program called_by The evidence states that gen_program() calls generate_directed_instr_stream() after init_gpr().

CITATIONS

8 sources

8 citations — click to expand

[1] riscv-dv is an open-source CHIPS Alliance random instruction generator for RISC-V processor verification. RISC-V source class riscv_asm_program_gen, the brain behind ...

[2] riscv_asm_program_gen generates complete RISC-V assembly programs, including initialization, instruction, data, stack, page-table, interrupt, and exception-handling sections. RISC-V source class riscv_asm_program_gen, the brain behind ...

[3] gen_program() is the main function that generates all sections of the program and calls other riscv_asm_program_gen functions in sequence. RISC-V source class riscv_asm_program_gen, the brain behind ...

[4] Before generate_directed_instr_stream(), gen_program() calls get_directed_instr_stream(), uses add_directed_instr_stream() to select directed-instruction ratios, generates the program header, and initializes GPRs. RISC-V source class riscv_asm_program_gen, the brain behind ...

[5] generate_directed_instr_stream() decides the ratio, inserts directed instruction streams, randomizes instructions, and selects rs1, rs2, and rd based on instruction type. RISC-V source class riscv_asm_program_gen, the brain behind ...

[6] The directed instruction generation flow helps produce assembly programs using GPRs x0 through x31, with support from riscv_instr.post_random(). RISC-V source class riscv_asm_program_gen, the brain behind ...

[7] After directed instruction stream generation, riscv_instr_sequence.generate_instr_stream uses the available instruction stream and convert2asm(), and main_program[hart].generate_instr_stream() converts the instruction stream to string format. RISC-V source class riscv_asm_program_gen, the brain behind ...

[8] The generation flow checks illegal and HINT instruction ratios, and if those ratios are zero then no illegal or HINT instructions are generated. RISC-V source class riscv_asm_program_gen, the brain behind ...