gen_program()
CodeArtifact`gen_program()` is the main RISC-V assembly program generation function described for the `riscv_asm_program_gen.sv` class in the CHIPS Alliance `riscv-dv` random instruction generator. It orchestrates header generation, GPR initialization, directed and random instruction stream generation, subprogram insertion, host-interface code, and trap-handling support to produce complete randomized RISC-V assembly programs for processor IP verification.
First seen 5/26/2026
Last seen 5/28/2026
Evidence 2 chunks
Wiki v1
WIKI
gen_program()
gen_program() is the main function described for generating all sections of a RISC-V assembly program in the riscv_asm_program_gen.sv class. It is part of the CHIPS Alliance open-source riscv-dv random instruction generator, which is used for RISC-V processor verification. [C1][C2]
Role in program generation
NEIGHBORHOOD
No graph connections found for this entity yet. It may appear in future ingestion runs.
explore full graph →RELATIONSHIPS
11 connectionsgen_program calls generate_directed_instr_stream to insert directed instruction streams.
gen_program uses gen_section to add host interface instructions and other sections.
gen_program calls push_gpr_to_kernel_stack to push GPRs to the kernel stack for trap handling.
gen_program is the main orchestration function implementing full RISC-V assembly program generation.
gen_program calls insert_sub_program to insert sub-programs into the instruction stream.
gen_program is the main function defined in the riscv_asm_program_gen class.
gen_program calls get_directed_instr_stream to select directed instruction streams.
gen_program calls add_directed_instr_stream to set the ratio of instruction generation.
gen_program calls gen_program_header to generate the program header.
gen_program calls init_gpr to initialize general purpose registers.
gen_program works with riscv_instruction_sequence to generate the full assembly program.
LINKED ENTITIES
7 linksriscv_instr_gen_config configured_by The evidence states that `riscv_instr_gen_config` is randomized before program generation and determines extensions, privilege modes, instruction counts, and instruction-disabling options.
gen_program_header calls The evidence states that `gen_program()` calls `gen_program_header()` to fill the `instr_stream` with header content.
gen_section calls The evidence states that `gen_program_header()` calls `gen_section("_start", str)` and that `gen_section()` is also used to add host-interface and trap-handler sections.
init_gpr calls The evidence states that `gen_program()` calls `init_gpr()` to initialize general-purpose registers with random values.
generate_directed_instr_stream calls The evidence states that `generate_directed_instr_stream()` is called to decide ratios, insert directed streams, randomize instructions, and select registers.
insert_sub_program calls The evidence states that if subprogram instructions are generated, `insert_sub_program(sub_program[hart], instr_stream)` is called.
push_gpr_to_kernel_stack calls The evidence states that `push_gpr_to_kernel_stack()` pushes general-purpose registers to the stack for trap handling.
CITATIONS
11 sources11 citations — click to expand
[1] CHIPS Alliance developed the open-source `riscv-dv` random instruction generator for RISC-V processor verification. RISC-V source class riscv_asm_program_gen, the brain behind ...
[2] `gen_program()` is the main function used to generate all sections of the program and calls other functions in `riscv_asm_program_gen` sequentially. RISC-V source class riscv_asm_program_gen, the brain behind ...
[3] `riscv_instr_gen_config` is randomized from `riscv_instr_base_test.sv` and controls extension, privilege mode, instruction counts, and instruction-disabling options such as `no_ebreak`, `no_dret`, `no_fence`, and `no_wfi`. RISC-V source class riscv_asm_program_gen, the brain behind ...
[4] `gen_program()` calls `get_directed_instr_stream()` and uses `add_directed_instr_stream()` to select directed-instruction generation ratios, with an example `riscv_jal_instr` ratio of `30/1000`. RISC-V source class riscv_asm_program_gen, the brain behind ...
[5] `gen_program()` calls `gen_program_header()`, which fills `instr_stream` with header content and calls `gen_section("_start", str)`. RISC-V source class riscv_asm_program_gen, the brain behind ...
[6] `gen_program()` calls `init_gpr()` to initialize general-purpose registers with random values. RISC-V source class riscv_asm_program_gen, the brain behind ...
[7] `generate_directed_instr_stream()` decides ratios, inserts directed instruction streams, randomizes instructions, and selects `rs1`, `rs2`, and `rd` based on instruction type, using GPRs `x0` through `x31` with help from `riscv_instr.post_random()`. RISC-V source class riscv_asm_program_gen, the brain behind ...
[8] `riscv_instr_sequence.generate_instr_stream()` uses `convert2asm()`, and `main_program[hart].generate_instr_stream()` converts the instruction stream to string format; illegal and HINT instructions are not generated when their ratios are zero. RISC-V source class riscv_asm_program_gen, the brain behind ...
[9] `gen_program()` and associated helpers produce complete RISC-V assembly programs with random instructions, random GPR selections, and different instruction patterns for robust IP verification. RISC-V source class riscv_asm_program_gen, the brain behind ...
[10] If subprogram instructions are generated, `insert_sub_program(sub_program[hart], instr_stream)` is called; after main and subprogram generation, host-interface code is added through `gen_section()` with content such as `write_tohost:`, `sw gp, tohost, t1`, and `_exit:`. RISC-V source class riscv_asm_program_gen, the brain behind ...
[11] `push_gpr_to_kernel_stack()` pushes general-purpose registers to the stack for trap handling, and `gen_section()` selects an `mtvec_handler` section containing `exception_handler` and `interrupt_handler` definitions. RISC-V source class riscv_asm_program_gen, the brain behind ...