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add_directed_instr_stream

CodeArtifact

add_directed_instr_stream is a function referenced in the riscv-dv riscv_asm_program_gen flow. The available evidence describes it as participating in selection of directed-instruction stream ratios during RISC-V assembly program generation, with an example log adding a riscv_jal_instr stream at a 30/1000 ratio.

First seen 5/26/2026
Last seen 5/28/2026
Evidence 1 chunks
Wiki v1

WIKI

Overview

add_directed_instr_stream is a code artifact referenced in the riscv_asm_program_gen.sv assembly-program generation flow used by the open-source CHIPS Alliance riscv-dv random instruction generator for RISC-V processor verification. The surrounding riscv_asm_program_gen class is described as generating complete RISC-V assembly programs, including initialization, instruction, data, stack, page-table, interrupt, and exception-handling sections. [C1]

Role in program generation

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NEIGHBORHOOD

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RELATIONSHIPS

2 connections
riscv_asm_program_gen part of → 95% 2e
add_directed_instr_stream is a function within riscv_asm_program_gen called by gen_program.
gen_program ← uses 100% 2e
gen_program calls add_directed_instr_stream to set the ratio of instruction generation.

CITATIONS

4 sources
4 citations — click to collapse
[1] riscv_asm_program_gen generates complete RISC-V assembly programs for riscv-dv verification flows, including sections such as initialization, instruction, data, stack, page table, interrupt, and exception handling. RISC-V source class riscv_asm_program_gen, the brain behind ...
[2] In the described gen_program flow, get_directed_instr_stream is called and the ratio of instruction generation is selected from add_directed_instr_stream. RISC-V source class riscv_asm_program_gen, the brain behind ...
[3] An example reporter message shows a directed instruction stream named riscv_jal_instr being added with ratio 30/1000 from riscv_asm_program_gen.sv. RISC-V source class riscv_asm_program_gen, the brain behind ...
[4] generate_directed_instr_stream is described as deciding ratios, inserting directed instruction streams, randomizing instructions, and selecting rs1, rs2, and rd based on instruction type. RISC-V source class riscv_asm_program_gen, the brain behind ...