get_directed_instr_stream

CodeArtifact

get_directed_instr_stream() is a function in the riscv_asm_program_gen assembly-program generation flow of riscv-dv. In the documented gen_program() sequence, it is called before program-header generation and is associated with selecting directed-instruction generation ratios through add_directed_instr_stream().

First seen 5/26/2026

Last seen 5/28/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

get_directed_instr_stream() is documented as part of the gen_program() execution flow in riscv_asm_program_gen.sv, the SystemVerilog UVM-based assembly program generator used by the CHIPS Alliance riscv-dv random instruction generator for RISC-V processor verification. The surrounding riscv_asm_program_gen class generates the complete RISC-V assembly program, including initialization, instruction, data, stack, page-table, interrupt, and exception-handling sections.

Role in program generation

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NEIGHBORHOOD

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RELATIONSHIPS

2 connections

riscv_asm_program_gen part of → 95% 2e

get_directed_instr_stream is a function within riscv_asm_program_gen called by gen_program.

gen_program ← uses 100% 2e

gen_program calls get_directed_instr_stream to select directed instruction streams.

LINKED ENTITIES

3 links

gen_program called_by The evidence explicitly says gen_program() calls get_directed_instr_stream().

add_directed_instr_stream uses_for_ratio_selection The evidence says get_directed_instr_stream() is followed by ratio selection from add_directed_instr_stream().

generate_directed_instr_stream related_directed_generation_step The evidence describes generate_directed_instr_stream() as a later function that decides ratios, inserts directed instruction streams, and randomizes instructions.

CITATIONS

7 sources

7 citations — click to expand

[1] riscv-dv is an open-source CHIPS Alliance random instruction generator for RISC-V processor verification. RISC-V source class riscv_asm_program_gen, the brain behind ...

[2] riscv_asm_program_gen.sv generates complete RISC-V assembly programs and covers sections such as initialization, instruction, data, stack, page table, interrupt, and exception handling. RISC-V source class riscv_asm_program_gen, the brain behind ...

[3] gen_program() is the main function for generating all sections of the assembly program. RISC-V source class riscv_asm_program_gen, the brain behind ...

[4] gen_program() calls get_directed_instr_stream(), and directed-instruction generation ratios are selected using add_directed_instr_stream(). RISC-V source class riscv_asm_program_gen, the brain behind ...

[5] An example directed stream log adds riscv_jal_instr with a ratio of 30/1000. RISC-V source class riscv_asm_program_gen, the brain behind ...

[6] generate_directed_instr_stream() later decides ratios, inserts directed instruction streams, randomizes instructions, and selects rs1, rs2, and rd according to instruction type. RISC-V source class riscv_asm_program_gen, the brain behind ...

[7] riscv_instr_gen_config is randomized from riscv_instr_base_test.sv and controls configuration such as RISC-V extension, privilege mode, instruction counts, and no_ebreak/no_dret/no_fence/no_wfi options. RISC-V source class riscv_asm_program_gen, the brain behind ...