insert_sub_program
CodeArtifact`insert_sub_program` is a code artifact invoked as `insert_sub_program(sub_program[hart], instr_stream)` during RISC-V assembly program generation. In the evidenced flow, it is called after sub-program instructions are selected or generated, and before host-interface and trap-handling sections are added.
First seen 5/26/2026
Last seen 5/28/2026
Evidence 1 chunks
Wiki v1
WIKI
Overview
insert_sub_program appears in the RISC-V assembly program generation flow as the function call:
insert_sub_program(sub_program[hart], instr_stream);
NEIGHBORHOOD
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2 connectionsinsert_sub_program is a function within riscv_asm_program_gen for inserting sub-programs.
gen_program calls insert_sub_program to insert sub-programs into the instruction stream.
LINKED ENTITIES
4 linksriscv_asm_program_gen used_within The evidence describes `insert_sub_program(sub_program[hart], instr_stream)` within the RISC-V assembly program generator flow associated with the `riscv_asm_program_gen` class.
gen_section sequence_precedes The evidence states that once main and sub-program generation is done, host-interface instructions are added by `gen_section`, placing `insert_sub_program` before that step in the flow.
gen_program part_of_generation_flow The evidence describes `gen_program()` and helper functions in the same class as generating the full RISC-V assembly program, the broader flow in which sub-program insertion is discussed.
push_gpr_to_kernel_stack sequence_precedes The evidence states that after host-interface instruction insertion, `push_gpr_to_kernel_stack()` pushes general-purpose registers to the stack for trap handling, placing it later in the documented flow.
CITATIONS
5 sources5 citations — click to expand
[1] `insert_sub_program` is called as `insert_sub_program(sub_program[hart], instr_stream)` after sub-program instruction generation or selection. RISC-V source class riscv_asm_program_gen, the brain behind ...
[2] After main and sub-program generation is complete, host-interface instructions such as `write_tohost`, `sw gp, tohost, t1`, and `_exit` are added by `gen_section`. RISC-V source class riscv_asm_program_gen, the brain behind ...
[3] `push_gpr_to_kernel_stack()` pushes general-purpose registers to the stack for trap handling. RISC-V source class riscv_asm_program_gen, the brain behind ...
[4] `gen_section()` selects an `mtvec_handler` section containing `exception_hander` and `interrupt_handler` definitions. RISC-V source class riscv_asm_program_gen, the brain behind ...
[5] `gen_program()` and related helpers generate complete RISC-V assembly programs with randomized instructions, randomized GPR selections, and varied instruction patterns. RISC-V source class riscv_asm_program_gen, the brain behind ...