riscv_instruction_sequence

CodeArtifact

riscv_instruction_sequence is identified as a collaborating code artifact in a RISC-V assembly program generation flow. In the cited flow, it works with gen_program(), riscv_asm_program_gen, base test classes, and helper classes to generate complete RISC-V assembly programs containing randomized instructions, randomized general-purpose register selections, and varied instruction patterns.

First seen 5/26/2026

Last seen 5/28/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

riscv_instruction_sequence is referenced as part of a RISC-V assembly instruction generation flow. The available evidence describes it as working together with gen_program(), functions in the same class, base test classes, and helper classes to generate a full RISC-V assembly language program. The generated programs contain random instructions, random general-purpose register selections for each instruction, and different instruction patterns.

Role in Program Generation

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NEIGHBORHOOD

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RELATIONSHIPS

3 connections

riscv-dv part of → 90% 2e

riscv_instruction_sequence is a helper class within riscv-dv.

gen_program ← uses 85% 1e

gen_program works with riscv_instruction_sequence to generate the full assembly program.

riscv_asm_program_gen ← uses 1e

riscv_asm_program_gen uses riscv_instruction_sequence to generate the full assembly program.

LINKED ENTITIES

1 links

riscv_asm_program_gen collaborates_with The evidence states that gen_program() and functions in the same class work together with riscv_instruction_sequence to generate complete RISC-V assembly programs; the article identifies that class as riscv_asm_program_gen.

CITATIONS

4 sources

4 citations — click to collapse

[1] riscv_instruction_sequence participates in generation of full RISC-V assembly programs RISC-V source class riscv_asm_program_gen, the brain behind ...

[2] The generated programs include randomized instructions, randomized general-purpose register choices, and different instruction patterns RISC-V source class riscv_asm_program_gen, the brain behind ...

[3] gen_program(), riscv_instruction_sequence, base test classes, and helper or configuration classes work together in the generation flow RISC-V source class riscv_asm_program_gen, the brain behind ...

[4] The surrounding flow includes sub-program insertion, host-interface instructions, and trap-handler setup through gen_section(), push_gpr_to_kernel_stack(), and mtvec_handler selection RISC-V source class riscv_asm_program_gen, the brain behind ...