interrupt and exception handling

Concept

In the provided evidence, interrupt and exception handling is described as one of the generated sections of a RISC-V assembly program produced by the riscv-dv `riscv_asm_program_gen` class for processor IP verification. The generated trap-handling support includes saving general-purpose registers to a kernel stack and emitting an `mtvec_handler` section that defines exception and interrupt handlers.

First seen 5/26/2026

Last seen 5/28/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

interrupt and exception handling is identified as one of the sections generated in a complete RISC-V assembly program by the riscv_asm_program_gen class in the CHIPS Alliance riscv-dv random instruction generator. The generated assembly program is used for RISC-V processor IP verification and is produced alongside other sections such as initialization routines, instruction sections, data sections, stack sections, and page tables.

Role in generated RISC-V assembly

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riscv_asm_program_gen ← implements 95% 2e

riscv_asm_program_gen generates interrupt and exception handling sections in the assembly program.

CITATIONS

6 sources

6 citations — click to expand

[1] Interrupt and exception handling is one of the sections generated in a complete RISC-V assembly program by `riscv_asm_program_gen`. RISC-V source class riscv_asm_program_gen, the brain behind ...

[2] `gen_program()` is the main function that generates all sections of the program. RISC-V source class riscv_asm_program_gen, the brain behind ...

[3] `push_gpr_to_kernel_stack()` pushes general-purpose registers to the stack for trap handling. RISC-V source class riscv_asm_program_gen, the brain behind ...

[4] `gen_section()` selects an `mtvec_handler` section that has `exception_handler` and `interrupt_handler` defined. RISC-V source class riscv_asm_program_gen, the brain behind ...

[5] CHIPS Alliance developed the open-source `riscv-dv` random instruction generator for RISC-V processor verification. RISC-V source class riscv_asm_program_gen, the brain behind ...

[6] Configuration randomization determines features such as RISC-V extension, supported privilege mode, instruction counts, and generation of break, debug-return, fence, and wait-for-interrupt instructions. RISC-V source class riscv_asm_program_gen, the brain behind ...