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interrupt and exception handling

Concept WIKI v1 · 5/26/2026

In the provided evidence, interrupt and exception handling is described as one of the generated sections of a RISC-V assembly program produced by the riscv-dv `riscv_asm_program_gen` class for processor IP verification. The generated trap-handling support includes saving general-purpose registers to a kernel stack and emitting an `mtvec_handler` section that defines exception and interrupt handlers.

Overview

interrupt and exception handling is identified as one of the sections generated in a complete RISC-V assembly program by the riscv_asm_program_gen class in the CHIPS Alliance riscv-dv random instruction generator. The generated assembly program is used for RISC-V processor IP verification and is produced alongside other sections such as initialization routines, instruction sections, data sections, stack sections, and page tables.

Role in generated RISC-V assembly

The riscv_asm_program_gen class generates full RISC-V assembly programs by coordinating multiple functions and helper classes. Its gen_program() function is described as the main function that generates all sections of the program. During program generation, the flow includes header generation, GPR initialization, directed and random instruction stream generation, optional subprogram insertion, host-interface code insertion, and trap-handling support.

Within this flow, interrupt and exception handling is tied to trap handling. The function push_gpr_to_kernel_stack() pushes general-purpose registers to the stack for trap handling. The program generator then uses gen_section() to select an mtvec_handler instruction section, and that mtvec_handler section has exception_handler and interrupt_handler definitions.

Technical elements mentioned in the evidence

  • push_gpr_to_kernel_stack() saves general-purpose registers to a stack for trap handling.
  • gen_section() is used by riscv_asm_program to select the mtvec_handler section.
  • The mtvec_handler section contains both exception_handler and interrupt_handler definitions.
  • Interrupt and exception handling is generated as part of a larger RISC-V assembly test program used for RISC-V IP verification.

Verification context

The evidence places interrupt and exception handling in the context of automated RISC-V assembly generation. CHIPS Alliance's open-source riscv-dv generator produces randomized assembly tests for RISC-V processor verification. Configuration randomization determines items such as the RISC-V extension, supported privilege mode, instruction counts for main and subprograms, and whether certain instruction types such as break, debug-return, fence, and wait-for-interrupt instructions are generated.

CITATIONS

6 sources
6 citations
[1] Interrupt and exception handling is one of the sections generated in a complete RISC-V assembly program by `riscv_asm_program_gen`. RISC-V source class riscv_asm_program_gen, the brain behind ...
[2] `gen_program()` is the main function that generates all sections of the program. RISC-V source class riscv_asm_program_gen, the brain behind ...
[3] `push_gpr_to_kernel_stack()` pushes general-purpose registers to the stack for trap handling. RISC-V source class riscv_asm_program_gen, the brain behind ...
[4] `gen_section()` selects an `mtvec_handler` section that has `exception_handler` and `interrupt_handler` defined. RISC-V source class riscv_asm_program_gen, the brain behind ...
[5] CHIPS Alliance developed the open-source `riscv-dv` random instruction generator for RISC-V processor verification. RISC-V source class riscv_asm_program_gen, the brain behind ...
[6] Configuration randomization determines features such as RISC-V extension, supported privilege mode, instruction counts, and generation of break, debug-return, fence, and wait-for-interrupt instructions. RISC-V source class riscv_asm_program_gen, the brain behind ...