page table
ConceptIn the provided RISC-V verification context, a page table is one of the assembly-program sections generated by the riscv-dv `riscv_asm_program_gen.sv` class as part of complete randomized RISC-V assembly tests for IP verification.
First seen 5/28/2026
Last seen 6/8/2026
Evidence 2 chunks
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Overview
In the available evidence, page table appears as a section of a generated RISC-V assembly program. The CHIPS Alliance open-source riscv-dv random instruction generator is used for RISC-V processor verification, and its riscv_asm_program_gen.sv class generates complete RISC-V assembly programs used to verify RISC-V IP.
Role in generated assembly programs
NEIGHBORHOOD
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2 connectionsriscv_asm_program_gen generates the page table section of the assembly program.
Page tables are part of the RISC-V privileged specification.
LINKED ENTITIES
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3 sources3 citations — click to collapse
[1] CHIPS Alliance developed the open-source riscv-dv random instruction generator for RISC-V processor verification, and `riscv_asm_program_gen.sv` generates complete RISC-V assembly programs used to verify RISC-V IP. RISC-V source class riscv_asm_program_gen, the brain behind ...
[2] The generated assembly program includes sections such as initialization routine, instruction section, data section, stack section, page table, interrupt handling, and exception handling, generated by functions in `riscv_asm_program_gen`. RISC-V source class riscv_asm_program_gen, the brain behind ...
[3] `gen_program()` is described as the main function for generating all sections of the program and as calling other `riscv_asm_program_gen` functions in sequence. RISC-V source class riscv_asm_program_gen, the brain behind ...