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riscv_asm_program_gen

CodeArtifact WIKI v1 · 5/26/2026

riscv_asm_program_gen is a SystemVerilog/UVM class in the riscv-dv random instruction generator that builds complete RISC-V assembly programs for processor IP verification. Its gen_program() flow composes program sections, initializes GPRs, inserts directed and randomized instruction streams, handles subprograms, and adds host-interface and trap-handling support.

Overview

riscv_asm_program_gen is described as the class behind complete RISC-V assembly-program generation in the open-source riscv-dv random instruction generator used for RISC-V processor verification. The generated random test can be run with a design IP, and the class can address customization of RISC-V GPRs or instructions. [C1]

The class generates multiple sections of an assembly program, including initialization, instruction, data, stack, page-table, interrupt-handling, and exception-handling sections. [C2]

Configuration dependency

Before program generation, riscv_instr_gen_config is randomized from riscv_instr_base_test.sv. That configuration determines the RISC-V extension being run, supported privilege mode, instruction counts for the main program and subprograms, and configuration flags such as no_ebreak, no_dret, no_fence, and no_wfi. [C3]

Main generation flow

gen_program() is the main function used to generate all program sections. When called by an upper layer, it invokes other functions in riscv_asm_program_gen sequentially. [C4]

A documented generation flow includes:

  1. Calling get_directed_instr_stream() and selecting directed-instruction generation ratios through add_directed_instr_stream(). [C5]
  2. Calling gen_program_header(), which fills the instr_stream string array with header content such as .include "user_init.s". [C6]
  3. Having gen_program_header() call gen_section("_start", str), which inserts header instructions into instr_stream. [C7]
  4. Calling init_gpr(), which initializes general-purpose registers with random values. [C8]
  5. Calling generate_directed_instr_stream(), which decides ratios, inserts directed instruction streams, randomizes instructions, and selects rs1, rs2, and rd based on instruction type. [C9]
  6. Using riscv_instr_sequence.generate_instr_stream() and convert2asm() to turn available instruction streams into assembly form. [C10]
  7. Calling main_program[hart].generate_instr_stream() from riscv_asm_program_gen to convert the instruction stream to string format. [C11]
  8. Inserting subprogram code with insert_sub_program(sub_program[hart], instr_stream) when subprogram instructions are generated. [C12]
  9. Adding host-interface-related instructions through gen_section, including labels and instructions such as write_tohost:, sw gp, tohost, t1, and _exit:. [C13]
  10. Calling push_gpr_to_kernel_stack() to push general-purpose registers to the stack for trap handling, and using gen_section() to select an mtvec_handler string that includes exception and interrupt handlers. [C14]

The flow also checks illegal-instruction and HINT-instruction ratios; when those ratios are zero, illegal or HINT instructions are not generated. [C15]

Generated output

The gen_program() function, related helper functions, riscv_instruction_sequence, base test classes, and configuration helpers together generate a full RISC-V assembly program. The resulting programs contain randomized instructions and randomized GPR selections, with different instruction patterns suitable for IP verification. [C16]

Role in verification

Within the described riscv-dv ecosystem, riscv_asm_program_gen is presented as a comprehensive utility for automating generation of RISC-V assembly programs. Its modular function calls and configuration support make it a central component for producing random assembly tests used in RISC-V IP verification. [C17]

LINKED ENTITIES

1 links
riscv_instr_gen_config USES

CITATIONS

17 sources
17 citations
[1] C1: riscv_asm_program_gen is a class in the open-source riscv-dv random instruction generator that generates complete RISC-V assembly programs for RISC-V IP verification and supports customization of RISC-V GPRs or instructions. RISC-V source class riscv_asm_program_gen, the brain behind ...
[2] C2: riscv_asm_program_gen generates assembly-program sections such as initialization, instruction, data, stack, page table, interrupt handling, and exception handling. RISC-V source class riscv_asm_program_gen, the brain behind ...
[3] C3: riscv_instr_gen_config is randomized from riscv_instr_base_test.sv and decides the extension, privilege mode, main and subprogram instruction counts, and flags such as no_ebreak, no_dret, no_fence, and no_wfi. RISC-V source class riscv_asm_program_gen, the brain behind ...
[4] C4: gen_program() is the main function that generates all sections of the program and calls other riscv_asm_program_gen functions sequentially. RISC-V source class riscv_asm_program_gen, the brain behind ...
[5] C5: gen_program() calls get_directed_instr_stream() and uses add_directed_instr_stream() to select directed-instruction generation ratios. RISC-V source class riscv_asm_program_gen, the brain behind ...
[6] C6: gen_program() calls gen_program_header(), which fills instr_stream with header content such as .include "user_init.s". RISC-V source class riscv_asm_program_gen, the brain behind ...
[7] C7: gen_program_header() calls gen_section("_start", str), inserting header instructions into instr_stream. RISC-V source class riscv_asm_program_gen, the brain behind ...
[8] C8: init_gpr() initializes general-purpose registers with random values. RISC-V source class riscv_asm_program_gen, the brain behind ...
[9] C9: generate_directed_instr_stream() decides ratios, inserts directed instruction streams, randomizes instructions, and selects rs1, rs2, and rd based on instruction type. RISC-V source class riscv_asm_program_gen, the brain behind ...
[10] C10: riscv_instr_sequence.generate_instr_stream() uses convert2asm() after the instruction stream is available. RISC-V source class riscv_asm_program_gen, the brain behind ...
[11] C11: main_program[hart].generate_instr_stream() is called from riscv_asm_program_gen to convert the instruction stream to string format. RISC-V source class riscv_asm_program_gen, the brain behind ...
[12] C12: insert_sub_program(sub_program[hart], instr_stream) is called when subprogram instructions are generated. RISC-V source class riscv_asm_program_gen, the brain behind ...
[13] C13: After main and subprogram generation, host-interface instructions are added through gen_section, including write_tohost, sw gp, tohost, t1, and _exit. RISC-V source class riscv_asm_program_gen, the brain behind ...
[14] C14: push_gpr_to_kernel_stack() pushes GPRs to the stack for trap handling, and gen_section() selects an mtvec_handler string containing exception and interrupt handlers. RISC-V source class riscv_asm_program_gen, the brain behind ...
[15] C15: If illegal-instruction or HINT-instruction ratios are zero, illegal or HINT instructions are not generated. RISC-V source class riscv_asm_program_gen, the brain behind ...
[16] C16: gen_program(), helper functions, riscv_instruction_sequence, base tests, and configuration helpers produce a complete RISC-V assembly program with randomized instructions and randomized GPR selections. RISC-V source class riscv_asm_program_gen, the brain behind ...
[17] C17: riscv_asm_program_gen is presented as a comprehensive utility in the riscv-dv verification ecosystem for automating RISC-V assembly-program generation with modular function calls and configuration support. RISC-V source class riscv_asm_program_gen, the brain behind ...